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Datasheet
M16C/5M Group, M16C/57 Group
RENESAS MCU
REJ03B0267-0101 Rev.1.01 Jul 23, 2010
1.
1.1
Overview
Features
The M16C/5M and M16C/57 Group's microcomputers (MCUs) are single-chip control units that utilize high-performance silicon gate CMOS technology with the M16C/60 Series CPU core. The M16C/5M Group and M16C/57 Group are available in 64-pin, 80-pin, and 100-pin plastic molded LQFP packages. The MCUs employ sophisticated instructions for a high level of efficiency and they are capable of executing instructions at high speed. The MCUs have the CAN module (M16C/5M Group) and LIN module, which makes them suitable for automotive control and factory automation LAN systems. In addition, the CPU core boasts a multiplier and DMAC for high-speed operation processing which makes it adequate for controlling office equipment, home appliances, and industrial equipment. The M16C/5M and M16C/57 Group's MCUs are a high-end microcontroller series in the M16C/5L and M16C/56 Group, featuring a single architecture as well as compatible pin assignments and peripheral functions. They have an on-chip E2PROM emulation data flash (E2dataFlash) which is a data flash with serial E2PROM.
1.1.1
Applications
Automotive, car audio, factory automation LAN system, etc.
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M16C/5M Group, M16C/57 Group
1. Overview
1.2
Specifications
Table 1.1 to Table 1.6 list specifications of the M16C/5M Group, M16C/57 Group.
Table 1.1
Item
Specifications (100-pin Package) (1/2)
Specification M16C/60 Series CPU Core (Multiplier: 16 x 16 unit: 16 x 16 + 32 32 bits)) Central processing unit * Basic instructions: 91 * Minimum instruction execution time: * Operating mode: Single-chip mode ROM, RAM, data flash, See Table 1.7 to Table 1.10. E2dataFlash Voltage detector Function 32 bits, Multiply-accumulate
CPU
Memory Voltage Detection
* 2 voltage detect points * 5 circuits (Main clock, sub clock, PLL frequency synthesizer, 125 kHz onchip oscillator, 40 MHz on-chip oscillator)
Clock
Clock generator
I/O Ports
Programmable I/O ports
Interrupts
Watchdog Timer
DMA
DMAC
* Oscillation stop detector: Main clock oscillator stop/restart detection * Frequency divide circuit: Divide-by-1, 2, 4, 8, or 16 selectable * Low-power consumption modes: Wait mode, stop mode * Real-time clock * 70 CMOS inputs/outputs, a pull-up resistor selectable * N-channel open drain ports: 1 * Interrupt vectors: 70 * External interrupt inputs: 13 (NMI, INT x 8, key input x 4) * Interrupt priority levels: 7 * 15 bits x 1 (with prescaler) * Automatic reset start function selectable * Dedicated 125 kHz on-chip oscillator for the watchdog timer contained * 4 channels, Cycle-steal transfer mode * Trigger sources: 50 * Transfer modes: 2 (single transfer, repeat transfer)
Timers
16-bit timer x 5 Timer mode, event counter mode, one-shot timer mode, pulse-width modulation (PWM) mode Timer A Two-phase pulse signal processing in event counter mode (two-phase encoder input) x 3 Programmable output mode x 3 16-bit timer x 6 Timer B Timer mode, event counter mode, pulse frequency measurement mode, pulse-width measurement mode Timer function for three- Three-phase motor control timer x 1 (timers A1, A2, A4, and B2 used) phase motor control On-chip dead time timer Timer S (Input capture/ output compare) Task monitoring timer Real-time clock
* 16-bit timer x 1 (base timer) * I/O: 8 channels
16-bit timer x 1 channel Count: seconds, minutes, hours, weeks 4 channels (UART, clock synchronous serial interface) 1 channels (UART, clock synchronous serial interface, I2C-bus, IEBus) 1 channel 10-bit resolution x 26 channels 8-bit resolution x 1 channel
Serial Interface
UART0 to UART4
Multi-master I2C-bus Interface A/D Converter D/A Converter
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1. Overview
Table 1.2
Item
Specifications (100-pin Package) (2/2)
Function Specification
CRC Calculator
* 1 circuit * CRC-CCITT (X16 + X12 + X5 + 1), CRC-16 (X16 + X15 + X2 + 1) compliant * MSB/LSB selectable
1 channel * Clock synchronous serial communication mode * 4-wire bus communication mode * Programmable character length: 8 to 16 bits 1 channel 32-slot message buffer x 2 channels or 1 channel (M16C/5M Group) (1)
Serial Bus Interface LIN Module CAN Module Flash Memory E2dataFlash Debug Functions Operating Frequency/Power Supply Voltage Current Consumption Operating Temperature Package
* Programming and erasure supply voltage: 3.0 to 5.5 V * Programming and erasure endurance: 1,000 times (program ROM 1,
program ROM 2)/10,000 times (data flash)
* Program security: ROM code protect, ID code check
Programming and erasure endurance: 100,000 (1) On-board flash rewrite function, address match x 4 32 MHz / 3.0 to 5.5 V Described in 31. "Electrical Characteristics" -40C to 85C -40C to 125C (1) 100-pin plastic mold LQFP: PLQP0100KB-A (Previous package code: 100P6Q-A)
Note: 1. Refer to Table 1.7 "M16C/5M Group Product List (J-Version)" to Table 1.10 "M16C/57 Group Product List (K-Version) for Operating Temperature, CAN Module, and E2dataFlash.
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1. Overview
Table 1.3
Item
Specifications (80-pin Package) (1/2)
Specification M16C/60 Series CPU Core (Multiplier: 16 x 16 unit: 16 x 16 + 32 32 bits)) Central processing unit * Basic instructions: 91 * Minimum instruction execution time: * Operating mode: Single-chip mode ROM, RAM, data flash, See Table 1.7 to Table 1.10. E2dataFlash Voltage detector Function 32 bits, Multiply-accumulate
CPU
Memory Voltage Detection
* 2 voltage detect points * 5 circuits (Main clock, sub clock, PLL frequency synthesizer, 125 kHz onchip oscillator, 40 MHz on-chip oscillator)
Clock
Clock generator
I/O Ports
Programmable I/O ports
Interrupts
Watchdog Timer
DMA
DMAC
* Oscillation stop detector: Main clock oscillator stop/restart detection * Frequency divide circuit: Divide-by-1, 2, 4, 8, or 16 selectable * Low-power consumption modes: Wait mode, stop mode * Real-time clock * 70 CMOS inputs/outputs, a pull-up resistor selectable * N-channel open drain ports: 1 * Interrupt vectors: 70 * External interrupt inputs: 11 (NMI, INT x 6, key input x 4) * Interrupt priority levels: 7 * 15 bits x 1 (with prescaler) * Automatic reset start function selectable * Dedicated 125 kHz on-chip oscillator for the watchdog timer contained * 4 channels, Cycle-steal transfer mode * Trigger sources: 43 * Transfer modes: 2 (single transfer, repeat transfer)
Timers
16-bit timer x 5 Timer mode, event counter mode, one-shot timer mode, pulse-width modulation (PWM) mode Timer A Two-phase pulse signal processing in event counter mode (two-phase encoder input) x 3 Programmable output mode x 3 16-bit timer x 3 Timer B Timer mode, event counter mode, pulse frequency measurement mode, pulse-width measurement mode Timer function for three- Three-phase motor control timer x 1 (timers A1, A2, A4, and B2 used) phase motor control On-chip dead time timer Timer S (Input capture/ output compare) Task monitoring timer Real-time clock
* 16-bit timer x 1 (base timer) * I/O: 8 channels
16-bit timer x 1 channel Count: seconds, minutes, hours, weeks 4 channels (UART, clock synchronous serial interface) 1 channels (UART, clock synchronous serial interface, I2C-bus, IEBus) 1 channel 10-bit resolution x 27 channels 8-bit resolution x 1 channel
Serial Interface
UART0 to UART4
Multi-master I2C-bus Interface A/D Converter D/A Converter
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1. Overview
Table 1.4
Item
Specifications (80-pin Package) (2/2)
Function Specification
CRC Calculator
* 1 circuit * CRC-CCITT (X16 + X12 + X5 + 1), CRC-16 (X16 + X15 + X2 + 1) compliant * MSB/LSB selectable
1 channel * Clock synchronous serial communication mode * 4-wire bus communication mode * Programmable character length: 8 to 16 bits 1 channel 32-slot message buffer x 2 channels or 1 channel (M16C/5M Group) (1)
Serial Bus Interface LIN Module CAN Module Flash Memory E2dataFlash Debug Functions Operating Frequency/Power Supply Voltage Current Consumption Operating Temperature Package
* Programming and erasure supply voltage: 3.0 to 5.5 V * Programming and erasure endurance: 1,000 times (program ROM 1,
program ROM 2)/10,000 times (data flash)
* Program security: ROM code protect, ID code check
Programming and erasure endurance: 100,000 (1) On-board flash rewrite function, address match x 4 32 MHz / 3.0 to 5.5 V Described in 31. "Electrical Characteristics" -40C to 85C -40C to 125C (1) 80-pin plastic mold LQFP: PLQP0080KB-A (Previous package code: 80P6Q-A)
Note: 1. Refer to Table 1.7 "M16C/5M Group Product List (J-Version)" to Table 1.10 "M16C/57 Group Product List (K-Version) for Operating Temperature, CAN Module, and E2dataFlash.
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1. Overview
Table 1.5
Item
Specifications (64-pin Package) (1/2)
Specification M16C/60 Series CPU Core (Multiplier: 16 x 16 unit: 16 x 16 + 32 32 bits)) Central processing unit * Basic instructions: 91 * Minimum instruction execution time: * Operating mode: Single-chip mode ROM, RAM, data flash, See Table 1.7 to Table 1.10. E2dataFlash Voltage detector Function 32 bits, Multiply-accumulate
CPU
Memory Voltage Detection
* 2 voltage detect points * 5 circuits (Main clock, sub clock, PLL frequency synthesizer, 125 kHz onchip oscillator, 40 MHz on-chip oscillator)
Clock
Clock generator
I/O Ports
Programmable I/O ports
Interrupts
Watchdog Timer
DMA
DMAC
* Oscillation stop detector: Main clock oscillator stop/restart detection * Frequency divide circuit: Divide-by-1, 2, 4, 8, or 16 selectable * Low-power consumption modes: Wait mode, stop mode * Real-time clock * 54 CMOS inputs/outputs, a pull-up resistor selectable * N-channel open drain ports: 1 * Interrupt vectors: 70 * External interrupt inputs: 11 (NMI, INT x 6, key input x 4) * Interrupt priority levels: 7 * 15 bits x 1 (with prescaler) * Automatic reset start function selectable * Dedicated 125 kHz on-chip oscillator for the watchdog timer contained * 4 channels, Cycle-steal transfer mode * Trigger sources: 41 * Transfer modes: 2 (single transfer, repeat transfer)
Timers
16-bit timer x 5 Timer mode, event counter mode, one-shot timer mode, pulse-width modulation (PWM) mode Timer A Two-phase pulse signal processing in event counter mode (two-phase encoder input) x 3 Programmable output mode x 3 16-bit timer x 3 Timer B Timer mode, event counter mode, pulse frequency measurement mode, pulse-width measurement mode Timer function for three- Three-phase motor control timer x 1 (timers A1, A2, A4, and B2 used) phase motor control On-chip dead time timer Timer S (Input capture/ output compare) Task monitoring timer Real-time clock
* 16-bit timer x 1 (base timer) * I/O: 8 channels
16-bit timer x 1 channel Count: seconds, minutes, hours, weeks 3 channels (UART, clock synchronous serial interface) 1 channels (UART, clock synchronous serial interface, I2C-bus, IEBus) 1 channel 10-bit resolution x 16 channels 8-bit resolution x 1 channel
Serial Interface
UART0 to UART3
Multi-master I2C-bus Interface A/D Converter D/A Converter
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1. Overview
Table 1.6
Item
Specifications (64-pin Package) (2/2)
Function Specification
CRC Calculator
* 1 circuit * CRC-CCITT (X16 + X12 + X5 + 1), CRC-16 (X16 + X15 + X2 + 1) compliant * MSB/LSB selectable
1 channel * Clock synchronous serial communication mode * 4-wire bus communication mode * Programmable character length: 8 to 16 bits 1 channel 32-slot message buffer x 2 channels or 1 channel (M16C/5M Group) (1)
Serial Bus Interface LIN Module CAN Module Flash Memory E2dataFlash Debug Functions Operating Frequency/Power Supply Voltage Current Consumption Operating Temperature Package
* Programming and erasure supply voltage: 3.0 to 5.5 V * Programming and erasure endurance: 1,000 times (program ROM 1,
program ROM 2)/10,000 times (data flash)
* Program security: ROM code protect, ID code check
Programming and erasure endurance: 100,000 (1) On-board flash rewrite function, address match x 4 32 MHz / 3.0 to 5.5 V Described in 31. "Electrical Characteristics" -40C to 85C -40C to 125C (1) 64-pin plastic mold LQFP: PLQP0064KB-A (Previous package code: 64P6Q-A)
Note: 1. Refer to Table 1.7 "M16C/5M Group Product List (J-Version)" to Table 1.10 "M16C/57 Group Product List (K-Version) for Operating Temperature, CAN Module, and E2dataFlash.
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1. Overview
1.3
Product List
Table 1.7 to Table 1.8 list product informations. Figure 1.1 shows part numbers, memory sizes, and packages. Figure 1.2 shows marking drawing (top view). Table 1.7 M16C/5M Group Product List (J-Version)
ROM Capacity Part Number
R5F35M23JFE R5F35M33JFF R5F35M73JFE R5F35M83JFF R5F35M16JFB R5F35M26JFE R5F35M36JFF R5F35M66JFB R5F35M76JFE R5F35M86JFF (P) (P) (P) (P) (P) (P) (P) (P) (P) (P) 4 Kbytes 256 Kbytes 16 Kbytes 4 Kbytes x 2 blocks 20 Kbytes 128 Kbytes 16 Kbytes 4 Kbytes x 2 blocks 4 Kbytes 12 Kbytes 96 Kbytes 16 Kbytes 4 Kbytes x 2 blocks Program ROM 1 Program ROM 2 Data flash
As of May. 2010
RAM
CAN
E2dataFlash Capacity 4 Kbytes 8 Kbytes
Package Name
PLQP0080KB-A PLQP0064KB-A PLQP0080KB-A PLQP0064KB-A PLQP0100KB-A PLQP0080KB-A PLQP0064KB-A PLQP0100KB-A PLQP0080KB-A PLQP0064KB-A PLQP0100KB-A PLQP0080KB-A PLQP0064KB-A PLQP0100KB-A PLQP0080KB-A
Remarks
---
---
1 channel
R5F35M1EJFB (P) R5F35M2EJFE (P) R5F35M3EJFF (P) R5F35M6EJFB (P) R5F35M7EJFE (P) R5F35M8EJFF (P) 4 Kbytes x 2 blocks 4 Kbytes 8 Kbytes R5F35MB3JFE (P) R5F35MC3JFF (P) R5F35ME3JFE (P) R5F35MF3JFF (P) R5F35MA6JFB (P) R5F35MB6JFE (P) R5F35MC6JFF (P) R5F35MD6JFB (P) R5F35ME6JFE (P) R5F35MF6JFF (P) 4 Kbytes 256 Kbytes 16 Kbytes 4 Kbytes x 2 blocks 20 Kbytes R5F35MAEJFB (D) R5F35MBEJFE (D) R5F35MCEJFF (D) R5F35MDEJFB (P) R5F35MEEJFE (P) R5F35MFEJFF (P) (D): Under development (P): Under planning The old package names are as follows: PLQP00100KB-A: 100P6Q-A PLQP0080KB-A: 80P6Q-A PLQP0064KB-A: 64P6Q-A 128 Kbytes 16 Kbytes 4 Kbytes x 2 blocks 4 Kbytes 12 Kbytes 96 Kbytes 16 Kbytes
---
Operating Temperature PLQP0080KB-A -40C to 85C PLQP0064KB-A PLQP0064KB-A PLQP0080KB-A PLQP0064KB-A PLQP0100KB-A PLQP0080KB-A PLQP0064KB-A 2 channels PLQP0100KB-A PLQP0080KB-A PLQP0064KB-A PLQP0100KB-A PLQP0080KB-A PLQP0064KB-A PLQP0100KB-A PLQP0080KB-A PLQP0064KB-A
---
---
---
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M16C/5M Group, M16C/57 Group
1. Overview
Table 1.8
Part Number
M6C/5M Group Product List (K-Version)
ROM Capacity
Program ROM 1 Program ROM 2 Data flash
As of May. 2010
RAM
CAN
E2dataFlash Capacity 4 Kbytes 8 Kbytes
Package Name
PLQP0080KB-A PLQP0064KB-A PLQP0080KB-A PLQP0064KB-A PLQP0100KB-A PLQP0080KB-A
Remarks
R5F35M23KFE (P) R5F35M33KFF (P) R5F35M73KFE (P) R5F35M83KFF (P) R5F35M16KFB (P) R5F35M26KFE (P) R5F35M36KFF (P) R5F35M66KFB (P) R5F35M76KFE (P) R5F35M86KFF (P) R5F35M1EKFB (P) R5F35M2EKFE (P) R5F35M3EKFF (P) R5F35M6EKFB (P) R5F35M7EKFE (P) R5F35M8EKFF (P) R5F35MB3KFE (P) R5F35MC3KFF (P) R5F35ME3KFE (P) R5F35MF3KFF (P) R5F35MA6KFB (P) R5F35MB6KFE (P) R5F35MC6KFF (P) R5F35MD6KFB (P) R5F35ME6KFE (P) R5F35MF6KFF (P) R5F35MAEKFB (P) R5F35MBEKFE (P) R5F35MCEKFF (P) R5F35MDEKFB (P) R5F35MEEKFE (P) R5F35MFEKFF (P) (D): Under development (P): Under planning The old package names are as follows: PLQP00100KB-A: 100P6Q-A PLQP0080KB-A: 80P6Q-A PLQP0064KB-A: 64P6Q-A 256 Kbytes 16 Kbytes 4 Kbytes x 2 blocks 128 Kbytes 16 Kbytes 4 Kbytes x 2 blocks 96 Kbytes 16 Kbytes 4 Kbytes x 2 blocks 256 Kbytes 16 Kbytes 4 Kbytes x 2 blocks 128 Kbytes 16 Kbytes 4 Kbytes x 2 blocks 96 Kbytes 16 Kbytes 4 Kbytes x 2 blocks
---
4 Kbytes 12 Kbytes
PLQP0064KB-A 1 channel PLQP0100KB-A PLQP0080KB-A PLQP0064KB-A PLQP0100KB-A
---
4 Kbytes 20 Kbytes
PLQP0080KB-A PLQP0064KB-A PLQP0100KB-A PLQP0080KB-A Operating Temperature PLQP0080KB-A -40C to 125C PLQP0064KB-A PLQP0064KB-A PLQP0080KB-A PLQP0064KB-A PLQP0100KB-A PLQP0080KB-A 12 Kbytes PLQP0064KB-A 2 channels PLQP0100KB-A PLQP0080KB-A PLQP0064KB-A PLQP0100KB-A
---
4 Kbytes 8 Kbytes
---
4 Kbytes
---
4 Kbytes 20 Kbytes
PLQP0080KB-A PLQP0064KB-A PLQP0100KB-A PLQP0080KB-A PLQP0064KB-A
---
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1. Overview
Table 1.9
M16C/57 Group Product List (J-Version)
ROM Capacity
Program ROM 1 Program ROM 2
As of May. 2010
RAM
CAN
Part Number
R5F35723JFE R5F35733JFF R5F35773JFE R5F35783JFF R5F35716JFB R5F35726JFE R5F35736JFF R5F35766JFB R5F35776JFE R5F35786JFF R5F3571EJFB R5F3572EJFE R5F3573EJFF R5F3576EJFB R5F3577EJFE R5F3578EJFF (P) (P) (P) (P) (P) (P) (P) (P) (P) (P) (P) (P) (P) (P) (P) (P)
Data flash
E2dataFlash Capacity 4 Kbytes 8 Kbytes
Package Name
PLQP0080KB-A PLQP0064KB-A PLQP0080KB-A PLQP0064KB-A PLQP0100KB-A PLQP0080KB-A
Remarks
96 Kbytes
16 Kbytes
4 Kbytes x 2 blocks
---
4 Kbytes
128 Kbytes 16 Kbytes
4 Kbytes x 2 blocks
12 Kbytes
PLQP0064KB-A N/A Operating Temperature PLQP0080KB-A -40C to 85C PLQP0064KB-A PLQP0100KB-A PLQP0100KB-A PLQP0080KB-A
---
4 Kbytes 256 Kbytes 16 Kbytes 4 Kbytes x 2 blocks 20 Kbytes
PLQP0064KB-A PLQP0100KB-A PLQP0080KB-A PLQP0064KB-A
---
(D): Under development (P): Under planning The old package names are as follows: PLQP00100KB-A: 100P6Q-A PLQP0080KB-A: 80P6Q-A PLQP0064KB-A: 64P6Q-A
Table 1.10
M16C/57 Group Product List (K-Version)
ROM Capacity
Program ROM 1 Program ROM 2
As of May. 2010
RAM
CAN
Part Number
R5F35723KFE R5F35733KFF R5F35773KFE R5F35783KFF R5F35716KFB R5F35726KFE R5F35736KFF R5F35766KFB R5F35776KFE R5F35786KFF R5F3571EKFB R5F3572EKFE R5F3573EKFF R5F3576EKFB R5F3577EKFE R5F3578EKFF (P) (P) (P) (P) (P) (P) (P) (P) (P) (P) (P) (P) (P) (P) (P) (P)
Data flash
E2dataFlash Capacity 4 Kbytes 8 Kbytes
Package Name
PLQP0080KB-A PLQP0064KB-A PLQP0080KB-A PLQP0064KB-A PLQP0100KB-A PLQP0080KB-A
Remarks
96 Kbytes
16 Kbytes
4 Kbytes x 2 blocks
---
4 Kbytes
128 Kbytes 16 Kbytes
4 Kbytes x 2 blocks
12 Kbytes
PLQP0064KB-A N/A Operating Temperature PLQP0080KB-A -40C to 125C PLQP0064KB-A PLQP0100KB-A PLQP0100KB-A PLQP0080KB-A
---
4 Kbytes 256 Kbytes 16 Kbytes 4 Kbytes x 2 blocks 20 Kbytes
PLQP0064KB-A PLQP0100KB-A PLQP0080KB-A PLQP0064KB-A
---
(D): Under development (P): Under planning The old package names are as follows: PLQP00100KB-A: 100P6Q-A PLQP0080KB-A: 80P6Q-A PLQP0064KB-A: 64P6Q-A
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1. Overview
MCU Part No.
R 5 F 3 5M 2 E J FE
Package type FB: PLQP0100KB-A (100P6Q-A) FE: PLQP0080KB-A (80P6Q-A) FF: PLQP0064KB-A (64P6Q-A) Property code J: Operating temperature -40C to 85C K: Operating temperature -40C to 125C Memory capacity Program ROM 1/RAM 3: 96 Kbytes/8 Kbytes 6: 128 Kbytes/12 Kbytes E: 256 Kbytes/20 Kbytes Pin / CAN module / E 2 data flash capacity 1: 100 pins / 1 channel / 4 Kbytes 2: 80 pins / 1 channel / 4 Kbytes 3: 64 pins / 1 channel / 4 Kbytes 57 Group has no CAN Module 6: 100 pins / 1 channel / -- 7: 80 pins / 1 channel / -- 8: 64 pins / 1 channel / -- A: 100 pins / 2 channels / 4 Kbytes B: 80 pins / 2 channels / 4 Kbytes C: 64 pins / 2 channels / 4 Kbytes D: 100 pins / 2 channels / -- E: 80 pins / 2 channels / -- F: 64 pins / 2 channels / -- Group Name 5M: M16C/5M Group, 57: M16C/57 Group 16-bit MCU Memory type F: Flash memory Renesas MCU Renesas semiconductor
Figure 1.1
Part Number, Memory Size, and Package
M16C R5F35M2EJFE XXXXXXX
Part number
(See Figure 1.1 "Part Number, Memory Size, and Package".)
Seven digit date code
Figure 1.2
Marking Diagram of Flash Memory Version (Top View)
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1. Overview
1.4
Block Diagrams
Figure 1.3 to Figure 1.5 show a block diagram of M16C/5M Group and M16C/57 Group.
8
8
8
8
8
8
I/O ports
Peripherals
Port P0
Port P1
Port P2
Port P3
Port P4
Port P5
Port P6
Timer (16-bit) Output (timer A): 5 Input (timer B): 6 Three-phase motor control circuit Timer S (Input capture/output compare) Time measurement: 8 channels Waveform generating: 8 channels Task monitoring timer (1 channel) Real-time clock A/D converter (10-bit x 26 channel) D/A converter (8-bit x 1 circuit) Serial bus interface (1 channel) Watchdog timer (15 bits, with the dedicated 125 kHz on-chip oscillator for the watchdog timer)
UART/clock synchronous serial interface (5 channels) DMAC (4 channels) Multi-master I2C-bus (1 channel) LIN module (1 channel) CAN module (32-slot message buffer, 2 or 1 channel) (M16C/5M Group only) (1) E2dataFlash
(1)
Clock generator
XIN-XOUT XCIN-XCOUT 40 MHz on-chip oscillator 125 kHz on-chip oscillator PLL frequency synthesizer CRC calculator (CCITT, CRC-16) Voltage detector Power-on reset On-chip debugger
8
Port P7 Port P8 Port P9
8 8 8
M16C/60 Series CPU core
R0H R1H R0L R1L R2 R3 R3 A0 A1 FB FB SB USP ISP INTB PC FLG
Memory ROM (1) RAM (1)
Port P10
8
Multiplier
Note: 1. The ROM size, RAM size, number of channels for the CAN module, and whether the E 2dataFlash is provided or not depend on the MCU type.
Figure 1.3
100-Pin Block Diagram
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1. Overview
8
8
8
8
I/O ports
Peripherals
Port P0
Port P1
Port P2
Port P3
Port P6
Timer (16-bit) Output (timer A): 5 Input (timer B): 3 Three-phase motor control circuit Timer S (Input capture/output compare) Time measurement: 8 channels Waveform generating: 8 channels Task monitoring timer (1 channel) Real-time clock A/D converter (10-bit x 27 channel) D/A converter (8-bit x 1 circuit) Serial bus interface (1 channel) Watchdog timer (15 bits, with the dedicated 125 kHz on-chip oscillator for the watchdog timer)
UART/clock synchronous serial interface (5 channels) DMAC (4 channels) Multi-master I2C-bus (1 channel) LIN module (1 channel) CAN module (32-slot message buffer, 2 or 1 channel) (M16C/5M Group only) (1) E2dataFlash
(1)
Clock generator
XIN-XOUT XCIN-XCOUT 40 MHz on-chip oscillator 125 kHz on-chip oscillator PLL frequency synthesizer
8
Port P7
8
CRC calculator (CCITT, CRC-16) Voltage detector Power-on reset
Port P8 Port P9
8
On-chip debugger
7
M16C/60 Series CPU core
R0H R1H R0L R1L R2 R3 R3 A0 A1 FB FB SB USP ISP INTB PC FLG
Memory ROM (1) RAM (1)
Port P10
8
Multiplier
Note: 1. The ROM size, RAM size, number of channels for the CAN module, and whether the E 2dataFlash is provided or not depend on the MCU type.
Figure 1.4
80-Pin Block Diagram
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1. Overview
4
3
8
4
I/O ports
Peripherals
Port P0
Port P1
Port P2
Port P3
Port P6
Timer (16-bit) Output (timer A): 5 Input (timer B): 3 Three-phase motor control circuit Timer S (Input capture/output compare) Time measurement: 8 channels Waveform generating: 8 channels Task monitoring timer (1 channel) Real-time clock
UART/clock synchronous serial interface (4 channels) DMAC(4 channels) Multi-master I2C-bus (1 channel) LIN module (1 channel) CAN module (32-slot message buffer, 2 or 1 channel) (M16C/5M Group only) (1) E2dataFlash
(1)
Clock generator
XIN-XOUT XCIN-XCOUT 40 MHz on-chip oscillator 125 kHz on-chip oscillator PLL frequency synthesizer
8
Port P7
8
CRC calculator (CCITT, CRC-16) Voltage detector Power-on reset
Port P8 Port P9
8
On-chip debugger A/D converter (10-bit x 16 channels) D/A converter (8-bit x 1 circuit) Serial bus interface (1 channel) Watchdog timer (15 bits, the dedicated 125 kHz on-chip oscillator for the watchdog timer)
4
Port P10
M16C/60 Series CPU core
R0H R1H R0L R1L R2 R3 R3 A0 A1 FB FB SB USP ISP INTB PC FLG
Memory ROM (1) RAM (1)
8
Multiplier
Note: 1. The ROM size, RAM size, number of channels for the CAN module, and whether the E 2dataFlash is provided or not depend on the MCU type.
Figure 1.5
64-Pin Block Diagram
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1. Overview
1.5
Pin Assignments
Figure 1.6 shows the pin assignments for the 100-pin package, Figure 1.7 shows the pin assignments for the 80-pin package, and Figure 1.8 shows the pin assignments for the 64-pin package.
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
P1_2 / AN2_2 P1_1 / AN2_1 P1_0 / AN2_0 P0_7 / AN0_7 P0_6 / AN0_6 P0_5 / AN0_5 P0_4 / AN0_4 P0_3 / AN0_3 P0_2 / AN0_2 P0_1 / AN0_1 P0_0 / AN0_0 P10_7 / AN_7 / KI3 P10_6 / AN_6 / KI2 P10_5 / AN_5 / KI1 P10_4 / AN_4 / KI0 P10_3 / AN_3 P10_2 / AN_2 P10_1 / AN_1 AVSS P10_0 / AN_0 VREF AVCC P9_7 / RXD4 / AN2_7 P9_6 / TXD4 / CTX0 (1) / AN2_6 P9_5 / CLK4 / CRX0 (1) / AN2_5
51
P1_3 / AN2_3 P1_4 P1_5 / INT3 / IDV / ADTRG P1_6 / INT4 / IDW P1_7 / INT5 / IDU / INPC1_7 P2_0 / OUTC1_0 / INPC1_0 / SDAMM P2_1 / OUTC1_1 / INPC1_1 / SCLMM P2_2 / OUTC1_2 / INPC1_2 P2_3 / / OUTC1_3 / INPC1_3 P2_4 / INT6 / OUTC1_4 / INPC1_4 P2_5 / INT7 / OUTC1_5 / INPC1_5 P2_6 / OUTC1_6 / INPC1_6 P2_7 / OUTC1_7 / INPC1_7 VSS P3_0 / CLK3 / SSCK0 VCC P3_1 / RXD3 / SSI0 P3_2 / TXD3 / SSO0 P3_3 / CTS3 / RTS3 / SCS0 P3_4 P3_5 P3_6 P3_7 P4_0 P4_1
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 3 4 5 6 7 8
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26
M16C/5M Group M16C/57 Group PLQP0100KB-A (100P6Q-A) (Top view)
P4_2 P4_3 P4_4 P4_5 P4_6 P4_7 P5_0 P5_1 P5_2 P5_3 P5_4 P5_5 P5_6 P5_7 P6_0 / RTCOUT / CTS0 / RTS0 P6_1 / CLK0 P6_2 / RXD0 P6_3 / TXD0 P6_4 / CTS1 / RTS1 P6_5 / CLK1 P6_6 / RXD1 P6_7 / TXD1 P7_0 / TXD2 / SDA2 / CTS1 / RTS1 / TA0OUT P7_1 / RXD2 / SCL2 / CLK1 / TA0IN / TB5IN P7_2 / CLK2 / TA1OUT / V / RXD1
Note: 1. Pins CTX0, CRX0, CTX1, and CRX1 are only available in the M16C/5M Group.
Figure 1.6
Pin Assignments for 100-Pin Package (Top View)
Set bits PACR2 to PACR0 in the PACR register to 100b before signals are input or output to individual pins after reset. When the PACR register is not set, signals are not input or output for some of the pins.
REJ03B0267-0101 Jul 23, 2010
Rev.1.01
P9_4 / TB4IN P9_3/DA0/TB3IN P9_2 / TB2IN / AN3_2 P9_1 / TB1IN / AN3_1 P9_0 / TB0IN / CLKOUT / AN3_0 NC CNVSS P8_7 / XCIN P8_6 / XCOUT RESET XOUT VSS XIN VCC P8_5 / NMI / SD P8_4 / INT2 / ZP P8_3 / INT1 P8_2 / INT0 P8_1 / TA4IN / U / TSUDB P8_0 / TA4OUT / U / TSUDA P7_7 / TA3IN / CRX1 (1) P7_6 / TA3OUT / CTX1 (1) P7_5 / TA2IN / W / LIN0IN P7_4 / TA2OUT / W / LIN0OUT P7_3 / CTS2 / RTS2 / TA1IN / V /TXD1
Page 15 of 156
M16C/5M Group, M16C/57 Group
1. Overview
Table 1.11
Pin No.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Pin Names, 100-Pin Package(1/2)
Port Interrupt Pin Timer Pin
TB4IN TB3IN TB2IN TB1IN TB0IN
Control Pin
Timer S Pin
UART/CAN/LIN/Serial Bus Interface Pin
Multimaster Analog Pin I2C-bus Pin
P9_4 P9_3 P9_2 P9_1 CLKOUT P9_0 NC CNVSS XCIN P8_7 XCOUT P8_6 RESET XOUT VSS XIN VCC P8_5 P8_4 P8_3 P8_2 P8_1 P8_0 P7_7 P7_6 P7_5 P7_4 P7_3 P7_2 P7_1 P7_0 P6_7 P6_6 P6_5 P6_4 P6_3 P6_2 P6_1 P6_0 P5_7 P5_6 P5_5 P5_4 P5_3 P5_2 P5_1 P5_0 P4_7 P4_6 P4_5 P4_4 P4_3 P4_2
DA0 AN3_2 AN3_1 AN3_0
NMI INT2 INT1 INT0
SD ZP
TA4IN/U TA4OUT/U TA3IN TA3OUT TA2IN/W TA2OUT/W TA1IN/V TA1OUT/V TA0IN/TB5IN TA0OUT
TSUDB TSUDA CRX1(1) CTX1 (1) LIN0IN LIN0OUT CTS2/RTS2/TXD1
CLK2/RXD1 RXD2/SCL2/CLK1 TXD2/SDA2/CTS1/RTS1 TXD1 RXD1 CLK1
CTS1/RTS1 TXD0 RXD0 CLK0 CTS0/RTS0
RTCOUT
Note:
1. There are pins CTX1 and CRX1 only in the M16C/5M Group.
REJ03B0267-0101 Jul 23, 2010
Rev.1.01
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M16C/5M Group, M16C/57 Group
1. Overview
Table 1.12
Pin No.
51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
Pin Names, 100-Pin Package(2/2)
Port
P4_1 P4_0 P3_7 P3_6 P3_5 P3_4 P3_3 P3_2 P3_1
Control Pin
Interrupt Pin
Timer Pin
Timer S Pin
UART/CAN/LIN/Serial Bus Interface Pin
Multimaster I2C- Analog Pin bus Pin
CTS3/RTS3/SCS0
TXD3/SSO0 RXD3/SSI0 CLK3/SSCK0
OUTC1_7/INPC1_7 OUTC1_6/INPC1_6 OUTC1_5/INPC1_5 OUTC1_4/INPC1_4 OUTC1_3/INPC1_3 OUTC1_2/INPC1_2 OUTC1_1/INPC1_1 OUTC1_0/INPC1_0 INPC1_7
VCC P3_0 VSS P2_7 P2_6 P2_5 P2_4 P2_3 P2_2 P2_1 P2_0 P1_7 P1_6 P1_5 P1_4 P1_3 P1_2 P1_1 P1_0 P0_7 P0_6 P0_5 P0_4 P0_3 P0_2 P0_1 P0_0 P10_7 P10_6 P10_5 P10_4 P10_3 P10_2 P10_1 AVSS P10_0 VREF AVCC P9_7 P9_6 P9_5 RXD4 TXD4/CTX0 (1) CLK4/CRX0 (1) AN2_7 AN2_6 AN2_5 AN_0
INT7 INT6
SCLMM SDAMM
INT5 INT4 INT3
IDU IDW IDV
ADTRG AN2_3 AN2_2 AN2_1 AN2_0 AN0_7 AN0_6 AN0_5 AN0_4 AN0_3 AN0_2 AN0_1 AN0_0 AN_7 AN_6 AN_5 AN_4 AN_3 AN_2 AN_1
KI3 KI2 KI1 KI0
Note:
1. Pins CTX0 and CRX0 are only available in the M16C/5M Group.
REJ03B0267-0101 Jul 23, 2010
Rev.1.01
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1. Overview
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
P0_7 / AN0_7 P1_0 / AN2_0 P1_1 / AN2_1 P1_2 / AN2_2 P1_3 / AN2_3 P1_4 P1_5 / INT3 / ADTRG / IDV P1_6 / INT4 / IDW P1_7 / INT5 / INPC1_7 / IDU P2_0 / OUTC1_0 / INPC1_0 / SDAMM P2_1 / OUTC1_1 / INPC1_1 / SCLMM P2_2 / OUTC1_2 / INPC1_2 P2_3 / OUTC1_3 / INPC1_3 P2_4 / OUTC1_4 / INPC1_4 P2_5 / OUTC1_5 / INPC1_5 P2_6 / OUTC1_6 / INPC1_6 P2_7 / OUTC1_7 / INPC1_7 P6_0 / RTCOUT / CTS0 / RTS0 P6_1 / CLK0 P6_2 / RXD0
P0_6 / AN0_6 P0_5 / AN0_5 P0_4 / AN0_4 P0_3 / AN0_3 P0_2 / AN0_2 P0_1 / AN0_1 P0_0 / AN0_0 P10_7 / AN_7 / KI3 P10_6 / AN_6 / KI2 P10_5 / AN_5 / KI1 P10_4 / AN_4 / KI0 P10_3 / AN_3 P10_2 / AN_2 P10_1 / AN_1 AVSS P10_0 / AN_0 VREF AVCC P9_7 / AN2_7 / RXD4 P9_6 / AN2_6 / TXD4
61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 10 11 12 13 14 15 16 17 18 19 20 1 2 3 4 5 6 7 8 9
40 39 38 37 36
M16C/5M Group M16C/57 Group PLQP0080KB-A (80P6Q-A) (Top view)
35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
P6_3 / TXD0 P3_0 / CLK3 / SSCK0 P3_1 / RXD3 / SSI0 P3_2 / TXD3 / SSO0 P3_3 / CTS3 / RTS3 / SCS0 P3_4 P3_5 P3_6 P3_7 P6_4 / CTS1 / RTS1 P6_5 / CLK1 P6_6 / RXD1 P6_7 / TXD1 P7_0 / TXD2 / SDA2 / TA0OUT / CTS1 / RTS1 P7_1 / RXD2 / SCL2 / TA0IN / CLK1 P7_2 / CLK2 / TA1OUT / V / RXD1 P7_3 / CTS2 / RTS2 / TA1IN / V / TXD1 P7_4 / TA2OUT / W / LIN0OUT P7_5 / TA2IN / W / LIN0IN P7_6 / TA3OUT / CTX1 (1)
Note: 1. Pins CTX0, CRX0, CTX1, and CRX1 are only available in the M16C/5M Group.
Figure 1.7
Pin Assignment for 80-Pin Package (Top View)
Set bits PACR2 to PACR0 in the PACR register to 011b before signals are input or output to individual pins after reset. When the PACR register is not set, signals are not input or output for some of the pins.
REJ03B0267-0101 Jul 23, 2010
Rev.1.01
P9_5 / AN2_5/ CLK4 P9_3 / AN2_4 /CTX0 (1) P9_2 / AN3_2 / TB2IN / CRX0 (1) P9_1 / AN3_1 / TB1IN / DA0 P9_0 / AN3_0 / TB0IN / CLKOUT CNVSS P8_7 / XCIN P8_6 / XCOUT RESET XOUT VSS XIN VCC P8_5 / NMI / SD P8_4 / INT2 / ZP P8_3 / INT1 P8_2 / INT0 P8_1 / TA4IN / U/ TSUDB P8_0 / TA4OUT / U/ TSUDA P7_7 / TA3IN / CRX1 (1)
Page 18 of 156
M16C/5M Group, M16C/57 Group
1. Overview
Table 1.13
Pin No. 1 2 3 4 5 6 7 8 9 Control pin
Pin Names, 80-Pin Package (1/2)
Port Interrupt Pin Timer Pin Timer S Pin UART/CAN/LIN/Serial Bus Interface Pin CLK4 CTX0 (1) TB2IN TB1IN TB0IN CRX0 (1) Multimaster I2C-bus pin Analog Pin
P9_5 P9_3 P9_2 P9_1 CLKOUT P9_0 CNVSS XCIN XCOUT RESET P8_7 P8_6
AN2_5 AN2_4 AN3_2 AN3_1/ DA0 AN3_0
10 XOUT 11 VSS 12 XIN 13 VCC 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 P8_5 P8_4 P8_3 P8_2 P8_1 P8_0 P7_7 P7_6 P7_5 P7_4 P7_3 P7_2 P7_1 P7_0 P6_7 P6_6 P6_5 P6_4 P3_7 P3_6 P3_5 P3_4 P3_3 P3_2 P3_1 P3_0 P6_3 CTS3/RTS3/SCS0 TXD3/SSO0 RXD3/SSI0 CLK3/SSCK0 TXD0 NMI INT2 INT1 INT0 TA4IN/U TA4OUT/U TA3IN TA3OUT TA2IN/W TA2OUT/W TA1IN/V TA1OUT/V TA0IN TA0OUT TSUDB TSUDA CRX1 (1) CTX1 (1) LIN0IN LIN0OUT CTS2/RTS2/TXD1 CLK2/RXD1 RXD2/SCL2/CLK1 TXD2/SDA2/CTS1/RTS1 TXD1 RXD1 CLK1 CTS1/RTS1 SD ZP
Note: 1. Pins CTX0, CRX0, CTX1 and CRX1 are only available in the M16C/5M Group.
REJ03B0267-0101 Jul 23, 2010
Rev.1.01
Page 19 of 156
M16C/5M Group, M16C/57 Group
1. Overview
Table 1.14
Pin No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 AVSS 76 77 VREF 78 AVCC 79 80 Control pin
Pin Names, 80-Pin Package (2/2)
Port Interrupt Pin Timer Pin Timer S Pin UART/CAN/LIN/Serial Bus Interface Pin RXD0 CLK0 RTCOUT OUTC1_7/INPC1_7 OUTC1_6/INPC1_6 OUTC1_5/INPC1_5 OUTC1_4/INPC1_4 OUTC1_3/INPC1_3 OUTC1_2/INPC1_2 OUTC1_1/INPC1_1 OUTC1_0/INPC1_0 INT5 INT4 INT3 IDU IDW IDV ADTRG AN2_3 AN2_2 AN2_1 AN2_0 AN0_7 AN0_6 AN0_5 AN0_4 AN0_3 AN0_2 AN0_1 AN0_0 AN_7 AN_6 AN_5 AN_4 AN_3 AN_2 AN_1 AN_0 INPC1_7 SCLMM SDAMM CTS0/RTS0 Multimaster I2C-bus pin Analog Pin
P6_2 P6_1 P6_0 P2_7 P2_6 P2_5 P2_4 P2_3 P2_2 P2_1 P2_0 P1_7 P1_6 P1_5 P1_4 P1_3 P1_2 P1_1 P1_0 P0_7 P0_6 P0_5 P0_4 P0_3 P0_2 P0_1 P0_0 P10_7 KI3 P10_6 KI2 P10_5 KI1 P10_4 KI0 P10_3 P10_2 P10_1 P10_0
P9_7 P9_6
RXD4 TXD4
AN2_7 AN2_6
REJ03B0267-0101 Jul 23, 2010
Rev.1.01
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M16C/5M Group, M16C/57 Group
1. Overview
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
P0_2 / AN0_2 P0_1 / AN0_1 P0_0 / AN0_0 P10_7 / AN_7 / KI3 P10_6 / AN_6 / KI2 P10_5 / AN_5 / KI1 P10_4 / AN_4 / KI0 P10_3 / AN_3 P10_2 / AN_2 P10_1 / AN_1 AVSS P10_0 / AN_0 VREF AVCC P9_3 / AN2_4 /CTX0 (1) P9_2 / AN3_2 / TB2IN / CRX0 (1)
33
P0_3 / AN0_3 P1_5 / INT3 / ADTRG / IDV P1_6 / INT4 / IDW P1_7 / INT5 / INPC1_7 / IDU P2_0 / OUTC1_0 / INPC1_0 / SDAMM P2_1 / OUTC1_1 / INPC1_1 / SCLMM P2_2 / OUTC1_2 / INPC1_2 P2_3 / OUTC1_3 / INPC1_3 P2_4 / OUTC1_4 / INPC1_4 P2_5 / OUTC1_5 / INPC1_5 P2_6 / OUTC1_6 / INPC1_6 P2_7 / OUTC1_7 / INPC1_7 P6_0 / RTCOUT / CTS0 / RTS0 P6_1 / CLK0 P6_2 / RXD0 P6_3 / TXD0
49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9
32 31 30
M16C/5M Group M16C/57 Group PLQP0064KB-A (64P6Q-A) (Top view)
29 28 27 26 25 24 23 22 21 20 19 18 17
P3_0 / CLK3 / SSCK0 P3_1 / RXD3 / SSI0 P3_2 / TXD3 / SSO0 P3_3 / CTS3 / RTS3 / SCS0 P6_4 / RTS1 / CTS1 P6_5 / CLK1 P6_6 / RXD1 P6_7 / TXD1 P7_0 / TXD2 / SDA2 / TA0OUT / CTS1 / RTS1 P7_1 / RXD2 / SCL2 / TA0IN / CLK1 P7_2 / CLK2 / TA1OUT / V / RXD1 P7_3 / CTS2 / RTS2 / TA1IN / V / TXD1 P7_4 / TA2OUT / W / LIN0OUT P7_5 / TA2IN / W / LIN0IN P7_6 / TA3OUT / CTX1 (1) P7_7 / TA3IN / CRX1 (1)
Note: 1. Pins CTX0, CRX0, CTX1, and CRX1 are only available in the M16C/5M Group.
Figure 1.8
Pin Assignments for 64-Pin Package (Top View)
Set bits PACR2 to PACR0 in the PACR register to 010b before signals are input or output to individual pins after reset. When the PACR register is not set, signals are not input or output for some of the pins.
REJ03B0267-0101 Jul 23, 2010
Rev.1.01
P9_1 / AN3_1 / TB1IN / DA0 P9_0 / AN3_0 / TB0IN / CLKOUT CNVSS P8_7 / XCIN P8_6 / XCOUT RESET XOUT VSS XIN VCC P8_5 / NMI / SD P8_4 / INT2 / ZP P8_3 / INT1 P8_2 / INT0 P8_1 / TA4IN / U / TSUDB P8_0 / TA4OUT / U / TSUDA
Page 21 of 156
M16C/5M Group, M16C/57 Group
1. Overview
Table 1.15
Pin No. Control pin
Pin Names, 64-Pin Package (1/2)
Port Interrupt Pin Timer Pin Timer S Pin UART/CAN/LIN/Serial Bus Interface Pin Multimaster I2C-bus Pin Analog Pin
1 2 3 4 5 6 7 8 9 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
P9_1 CLKOUT P9_0 CNVSS XCIN XCOUT RESET XOUT VSS XIN P8_5 P8_4 P8_3 P8_2 P8_1 P8_0 P7_7 P7_6 P7_5 P7_4 P7_3 P7_2 P7_1 P7_0 P6_7 P6_6 P6_5 P6_4 P3_3 P3_2 NMI INT2 INT1 INT0 P8_7 P8_6
TB1IN TB0IN
AN3_1/ DA0 AN3_0
10 VCC SD ZP
TA4IN/U TA4OUT/U TA3IN TA3OUT TA2IN/W TA2OUT/W TA1IN/V TA1OUT/V TA0IN TA0OUT
TSUDB TSUDA CRX1 (1) CTX1 (1) LIN0IN LIN0OUT CTS2/RTS2/TXD1 CLK2/RXD1 RXD2/SCL2/CLK1 TXD2/SDA2/CTS1/RTS1 TXD1 RXD1 CLK1 CTS1/RTS1 CTS3/RTS3 / SCS0 TXD3 / SSO0
Note:
1. Pins CTX1 and CRX1 are only available in the M16C/5M Group.
REJ03B0267-0101 Jul 23, 2010
Rev.1.01
Page 22 of 156
M16C/5M Group, M16C/57 Group
1. Overview
Table 1.16
Pin No. 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 AVSS 60 61 VREF 62 AVCC 63 64 Control pin
Pin Names, 64-Pin Package (2/2)
Port Interrupt Pin Timer Pin Timer S Pin UART/CAN/LIN/Serial Bus Interface Pin RXD3 / SSI0 CLK3 / SSCK0 TXD0 RXD0 CLK0 RTCOUT OUTC1_7/INPC1_7 OUTC1_6/INPC1_6 OUTC1_5/INPC1_5 OUTC1_4/INPC1_4 OUTC1_3/INPC1_3 OUTC1_2/INPC1_2 OUTC1_1/INPC1_1 OUTC1_0/INPC1_0 INT5 INT4 INT3 IDU IDW IDV ADTRG AN0_3 AN0_2 AN0_1 AN0_0 AN_7 AN_6 AN_5 AN_4 AN_3 AN_2 AN_1 AN_0 INPC1_7 SCLMM SDAMM CTS0/RTS0 Multimaster I2C-bus pin Analog Pin
P3_1 P3_0 P6_3 P6_2 P6_1 P6_0 P2_7 P2_6 P2_5 P2_4 P2_3 P2_2 P2_1 P2_0 P1_7 P1_6 P1_5 P0_3 P0_2 P0_1 P0_0 P10_7 KI3 P10_6 KI2 P10_5 KI1 P10_4 KI0 P10_3 P10_2 P10_1 P10_0
P9_3 P9_2 TB2IN
CTX0 (1) CRX0 (1)
AN2_4 AN3_2
Note: 1. Pins CTX0 and CRX0 are only available in the M16C/5M Group.
REJ03B0267-0101 Jul 23, 2010
Rev.1.01
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M16C/5M Group, M16C/57 Group
1. Overview
1.6
Pin Functions
Pin Functions (64-Pin, 80-Pin, and 100-Pin Packages)
Pin Name VCC, VSS AVCC, AVSS RESET CNVSS XIN I/O I I I I I O I O O I I I I/O I I I O I O I O I/O I O I/O I/O I/O Description Apply 3.0 V to 5.5 V to the VCC pin and 0 V to the VSS pin. Power supply for the A/D converter and D/A converter. Pins AVCC and AVSS should be connected to VCC and VSS, respectively. Driving this pin low resets the MCU. Connect to VSS via a resistor. Input/output for the main clock oscillator. Connect a ceramic resonator or crystal oscillator between XIN and XOUT. (1) To apply an external clock, connect it to XIN and leave XOUT open. When XIN is not used, connect XIN to VCC pin and leave XOUT open. Input/output for the sub clock oscillator. Connect a crystal oscillator between XCIN and XCOUT. (1) This pin outputs the clock having the same frequency as f1, f8, f32, or fC. Input for INT interrupt Input for NMI Input for the key input interrupt Timers A0 to A4 input/output Timers A0 to A4 input Input for Z-phase Timers B0 to B2 input Output for three-phase motor control timer Input for three-phase motor control timer Output for real-time clock Input to control data transmission Output to control data reception Transfer clock input/output Serial data input Serial data output Serial data input/output Transfer clock input/output Serial data input/output Transfer clock input/output
Table 1.17
Power supply Analog power supply Reset input CNVSS
Signal Name
Main clock input
Main clock output Sub clock input Sub clock output Clock output INT interrupt input NMI input Key input interrupt
XOUT XCIN XCOUT CLKOUT INT0 to INT5 NMI KI0 to KI3 TA0OUT to TA4OUT
Timer A
TA0IN to TA4IN ZP TB0IN to TB2IN
Timer B
Three-phase motor U,U,V,V,W,W control timer IDU, IDW, IDV, SD Real-time clock RTCOUT CTS0 to CTS3 RTS0 to RTS3 Serial interface UART0 to UART3 CLK0 to CLK3 RXD0 to RXD3 TXD0 to TXD3 UART2 I2C mode Multi-master I2C bus SDA2 SCL2 SDAMM SCLMM
Note: 1. Please contact the oscillator manufacturer for oscillation characteristic.
REJ03B0267-0101 Jul 23, 2010
Rev.1.01
Page 24 of 156
M16C/5M Group, M16C/57 Group
1. Overview
Table 1.18
Pin Functions (64-Pin, 80-Pin, and 100-Pin Packages)
Signal Name
Reference voltage input VREF
Pin Name
I/O
I
Description
Reference voltage input for the A/D converter and D/A converter.
A/D converter
AN_0 to AN_7 AN0_0 to AN0_3 AN3_0 to AN3_2 ADTRG INPC1_0 to INPC1_7
I I I O I I O O O I O I I/O I
Analog input Input for an external trigger Input for time measurement function Output for waveform generating function Two-phase pulse input Receive data input for CAN communication Transmit data output for CAN communication Output for the D/A converter Transmit data output for LIN communication Receive data input for LIN communication Serial data output Serial data input Input/output for transmit/receive clock Input to control the serial interface CMOS I/O ports. A direction register determines whether each pin is used as an input port or an output port. For input ports, pull-up resistor is selectable for every unit of 4 bits. However, P8_5 output is N-channel open drain output and does not have a pull-up resistor. Port P8_5 shares the pin with NMI, so that the NMI input level can be read from the P8 register P8_5 bit.
Timer S
OUTC1_0 to OUTC1_7 TSUDA, TSUDB CRX0, CRX1 CTX0, CTX1 DA0 LIN0OUT LIN0IN SSO0 SSI0 SSCK0 SCS0 P0_0 to P0_3 P1_5 to P1_7 P2_0 to P2_7 P3_0 to P3_3 P6_0 to P6_7 P7_0 to P7_7 P8_0 to P8_7 P9_0 to P9_3 P10_0 to P10_7
CAN Module (1) D/A converter LIN module
Serial bus interface
I/O port
I/O
Note:
1. There is the CAN module only in the M16C/5M Group.
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1. Overview
Table 1.19
Pin Functions (100-Pin Package Only)
Signal Name
INT interrupt input Timer B I/O port
Pin Name
INT6 and INT7 TB3IN to TB5IN P4_0 to P4_7 P5_0 to P5_7 P9_4
I/O
I Input for INT interrupt Timers B3 to B5 input
Description
I
CMOS I/O ports. A direction register determines whether each
I/O pin is used as an input port or an output port. For input ports,
pull-up resistor is selectable for every unit of 4 bits.
Table 1.20
A/D converter
Pin Functions (80-Pin and 64-Pin Package Only)
Signal Name
Pin Name
AN2_4
I/O I
Analog input
Description
Table 1.21
Pin Functions (100-Pin and 80-Pin Package Only)
Signal Name
CLK4 Serial Interface UART4 RXD4 TXD4 A/D converter
Pin Name
I/O I O I
Serial data input Serial data output Analog input
Description
I/O Transfer clock input/output
AN0_4 to AN0_7 AN2_0 to AN2_3 AN2_5 to AN2_7 P0_4 to P0_7 P1_0 to P1_4 P3_4 to P3_7 P9_5 to P9_7
CMOS I/O ports. A direction register determines whether each
I/O port
I/O pin is used as an input port or an output port. For input ports,
Pull-up resistor is selectable for every unit of 4 bits.
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2. Central Processing Unit (CPU)
2.
Central Processing Unit (CPU)
Figure 2.1 shows the CPU registers. Seven registers (R0, R1, R2, R3, A0, A1, and FB) out of 13 compose a register bank, and there are two register banks.
b31
b15
b8 b7
b0
R2 R3
R0H (upper bits of R0) R1H (upper bits of R1)
R0L (lower bits of R0) R1L (lower bits of R1)
Data registers (1)
R2 R3 A0 A1 FB
b19 b15 b0
Address registers (1) Frame base registers (1)
INTBH
INTBL
Interrupt table register
INTBH is the 4 upper bits of the INTB register and INTBL is the 16 lower bits.
b19 b0
PC
b15 b0
Program counter
USP ISP SB
b15 b0
User stack pointer Interrupt stack pointer Static base register
FLG
b15 b8 b7 b0
Flag register
IPL
U
I
OB
S
Z
D
C
Carry flag Debug flag Zero flag Sign flag Register bank select flag Overflow flag Interrupt enable flag Stack pointer select flag Reserved area Processor interrupt priority level Reserved area Note: 1. These registers compose a register bank. There are two register banks.
Figure 2.1
CPU Registers
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2. Central Processing Unit (CPU)
2.1
Data Registers (R0, R1, R2, and R3)
R0, R1, R2, and R3 are 16-bit registers used for transfer, arithmetic, and logic operations. R0 and R1 can be split into upper (R0H/R1H) and lower (R0L/R1L) bits to be used separately as 8-bit data registers. R0 can be combined with R2, and R3 can be combined with R1 and be used as 32-bit data registers R2R0 and R3R1, respectively.
2.2
Address Registers (A0 and A1)
A0 and A1 are 16-bit registers used for indirect addressing, relative addressing, transfer, arithmetic, and logic operations. A0 can be combined with A1 and used as a 32-bit address register (A1A0).
2.3
Frame Base Register (FB)
FB is a 16-bit register that is used for FB relative addressing.
2.4
Interrupt Table Register (INTB)
INTB is a 20-bit register that indicates the start address of a relocatable interrupt vector table.
2.5
Program Counter (PC)
The PC is 20 bits wide and indicates the address of the next instruction to be executed.
2.6
User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
The USP and ISP stack pointers (SP) are each comprised of 16 bits. The U flag is used to switch between USP and ISP.
2.7
Static Base Register (SB)
SB is a 16-bit register used for SB relative addressing.
2.8
Flag Register (FLG)
FLG is an 11-bit register that indicates the CPU state.
2.8.1
Carry Flag (C Flag)
The C flag retains a carry, borrow, or shift-out bit generated by the arithmetic/logic unit.
2.8.2
Debug Flag (D Flag)
The D flag is for debugging only. Set it to 0.
2.8.3
Zero Flag (Z Flag)
The Z flag becomes 1 when an arithmetic operation results in 0. Otherwise, it becomes 0.
2.8.4
Sign Flag (S Flag)
The S flag becomes 1 when an arithmetic operation results in a negative value. Otherwise, it becomes 0.
2.8.5
Register Bank Select Flag (B Flag)
Register bank 0 is selected when the B flag is 0. Register bank 1 is selected when this flag is 1.
2.8.6
Overflow Flag (O Flag)
The O flag becomes 1 when an arithmetic operation results in an overflow. Otherwise, it becomes 0.
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2.8.7
Interrupt Enable Flag (I Flag)
The I flag enables maskable interrupts. Maskable interrupts are disabled when the I flag is 0, and enabled when it is 1. The I flag becomes 0 when an interrupt request is accepted.
2.8.8
Stack Pointer Select Flag (U Flag)
ISP is selected when the U flag is 0. USP is selected when the U flag is 1. The U flag becomes 0 when a hardware interrupt request is accepted, or the INT instruction of software interrupt number 0 to 31 is executed.
2.8.9
Processor Interrupt Priority Level (IPL)
IPL is 3 bits wide and assigns processor interrupt priority levels from 0 to 7. If a requested interrupt has higher priority than IPL, the interrupt request is enabled.
2.8.10
Reserved Areas
Only set these bits to 0. The read value is undefined.
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3. Memory
3.
Memory
Special function registers (SFRs) are allocated from address 00000h to 003FFh and from 0D000h to 0D7FFh. Peripheral function control registers are located here. All blank spaces within SFRs are reserved, so do not access any blank spaces. The internal RAM is allocated from address 00400h to superior direction. For example, a 8-Kbyte internal RAM is addressed from 00400h to 023FFh. The internal RAM is used not only for data storage but also for stack area when subroutines are called or when interrupt request are acknowledged. The internal ROM is flash memory. Four internal ROM areas are available: E 2 dataFlash, data flash, program ROM 1, and program ROM 2. The data flash is addressed from 0E000h to 0FFFFh. This data flash space is used not only for data storage but also for program storage. Program ROM 2 is assigned addresses 10000h to 13FFFh. Program ROM 1 is assigned addresses FFFFFh to inferior direction. For example, the 64-Kbyte program ROM 1 space has addresses F0000h to FFFFFh. The E2dataFlash is not shown in the memory map because the E2FA register value is used as an address. The E2dataFlash cannot be used for program storage. Whether the E2dataFlash is provided or not depends on the product. The special page vectors are assigned addresses FFE00h to FFFD7h. They are used for the JMPS instruction and JSRS instruction. Refer to the M16C/60, M16C/20, M16C/Tiny Series Software Manual for details. The fixed vector table for interrupts, ID code write address, OFS1 address and OSF2 address are assigned addresses FFFDBh to FFFFFh. The 256 bytes beginning with the start address set in the INTB register compose the relocatable vector table for interrupts.
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3. Memory
00000h 00400h XXXXXh
SFRs Internal RAM Reserved (1)
Relocatable vector table
256 bytes beginning with the start address set in the INTB register
0D000h 0D800h 0E000h Internal RAM Capacity 8 Kbytes 12 Kbytes 20 Kbytes XXXXXh 023FFh 033FFh 053FFh 10000h 14000h
SFRs Reserved (1) Internal ROM (Data flash) Internal ROM (Program ROM 2) 13000h 13FF0h User boot code area 13FFFh On-chip debugger monitor area
Reserved (1) Internal ROM Capacity 96 Kbytes 128 Kbytes 256 Kbytes YYYYYh E8000h E0000h C0000h FFFFFh YYYYYh Internal ROM (Program ROM 1) FFFFFh FFE00h FFFD8h FFFDBh Special page vector table Reserved (2) Fixed vector table ID code write address OFS1 address OSF2 address
The above assumes the following: -The PM10 bit in the PM1 register is set to 1 (addresses from 0E000h to 0FFFFh are used as data flash) -The PRG2C0 bit in the PRG2C register is set to 0 (program ROM 2 enabled)
Notes:
1. Do not access these reserved areas. 2. Do not change the data from FFh.
Figure 3.1
Memory Map
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4. Special Function Registers (SFRs)
4.
4.1
Special Function Registers (SFRs)
SFRs
An SFR is a control register for a peripheral function.
Table 4.1 Address 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001Ah 001Bh 001Ch 001Dh 001Eh 001Fh SFR Information (1) (1) Register Symbol Reset Value
Processor Mode Register 0 Processor Mode Register 1 System Clock Control Register 0 System Clock Control Register 1
PM0 PM1 CM0 CM1
00h
0000 1000b 0100 1000b 0010 0000b
Protect Register Oscillation Stop Detection Register
PRCR CM2
00h 0X00 0010b (3)
Program 2 Area Control Register Peripheral Clock Select Register
PRG2C PCLKR
XXXX XX00b 0000 0011b
Clock Prescaler Reset Flag
CPSRF
0XXX XXXXb
Reset Source Determine Register Voltage Detector 2 Flag Register Voltage Detector Operation Enable Register
RSTFR VCR1 VCR2
XX0X 001Xb
(hardware reset) (4) 0000 1000b (2) 000X 0000b (2, 5) 001X 0000b (2, 6)
0X01 X010b
PLL Control Register 0
PLC0
Processor Mode Register 2
PM2
XX00 0X01b X: Undefined
Notes: 1. The blank areas are reserved. No access is allowed. 2. Software reset, watchdog timer reset, oscillator stop detect reset, and voltage monitor 2 reset do not affect the following registers: the VCR1 register and the VCR2 register. 3. Oscillator stop detect reset does not affect bits CM20, CM21, and CM27. 4. The state of bits in the RSTFR register depends on the reset type. 5. This is the reset value when the LVDAS bit of the OFS1 address is 1 during hardware reset. 6. This is the reset value after voltage monitor 0 reset, power-on reset, or when the LVDAS bit of the OFS1 address is 0 during hardware reset.
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Table 4.2 Address 0020h 0021h 0022h 0023h 0024h 0025h 0026h 0027h 0028h 0029h 002Ah 002Bh 002Ch 002Dh 002Eh 002Fh 0030h 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh
SFR Information (2) (1) Register Symbol Reset Value
40 MHz On-Chip Oscillator Control Register 0 40 MHz On-Chip Oscillator Control Register 2 Voltage Monitor Function Select Register Voltage Detector 2 Level Select Register
FRA0 FRA2 VWCE VD2LS
XXXX XX00b 0XX0 X000b 00h 0000 0100b
(2)
Voltage Monitor 0 Control Register
VW0C
1100 1X10b (3, 4) 1100 1X11b (3, 5) 1000 0X10b (3, 6)
Voltage Monitor 2 Control Register
VW2C
X: Undefined Notes: 1. The blank areas are reserved. No access is allowed. 2. Hardware reset, power-on reset, voltage monitor 0 reset, or voltage monitor 2 reset. 3. Software reset, watchdog timer reset, oscillator stop detect reset, and voltage monitor 2 reset do not affect the following registers or bit: the VW0C register, and bits VW2C2 and VW2C3 in the VW2C register. 4. This is the reset value when the LVDAS bit of the OFS1 address is 1 during hardware reset 5. This is the reset value after voltage monitor 0 reset, power-on reset, or when the LVDAS bit of the OFS1 address is 0 during hardware reset. 6. This is the reset value after hardware reset, power-on reset, or voltage monitor 0 reset
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Table 4.3 Address 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h 0058h 0059h 005Ah 005Bh 005Ch 005Dh 005Eh 005Fh Note: 1.
SFR Information (3) (1) Register E2dataFlash Interrupt Control Register INT7 Interrupt Control Register Serial Bus Interface 0 Interrupt Control Register INT6 Interrupt Control Register LIN0 Interrupt Control Register INT3 Interrupt Control Register Timer B5 Interrupt Control Register Timer B4 Interrupt Control Register Timer B3 Interrupt Control Register INT5 Interrupt Control Register INT4 Interrupt Control Register UART2 Bus Collision Detection Interrupt Control Register Task Monitoring Timer Interrupt Control Register DMA0 Interrupt Control Register DMA1 Interrupt Control Register Key Input Interrupt Control Register A/D Conversion Interrupt Control Register UART2 Transmit Interrupt Control Register UART2 Receive Interrupt Control Register UART0 Transmit Interrupt Control Register LIN0 Low Detection Interrupt Control Register UART0 Receive Interrupt Control Register UART1 Transmit Interrupt Control Register UART1 Receive Interrupt Control Register Timer A0 Interrupt Control Register Timer A1 Interrupt Control Register Timer A2 Interrupt Control Register Timer A3 Interrupt Control Register Timer A4 Interrupt Control Register Timer B0 Interrupt Control Register Timer B1 Interrupt Control Register Timer B2 Interrupt Control Register INT0 Interrupt Control Register INT1 Interrupt Control Register INT2 Interrupt Control Register Symbol E2FIC INT7IC SS0IC INT6IC LIN0IC INT3IC TB5IC TB4IC TB3IC INT5IC INT4IC BCNIC TMOSIC DM0IC DM1IC KUPIC ADIC S2TIC S2RIC S0TIC L0WIC S0RIC S1TIC S1RIC TA0IC TA1IC TA2IC TA3IC TA4IC TB0IC TB1IC TB2IC INT0IC INT1IC INT2IC Reset Value XXXX X000b XX00 X000b XX00 X000b XX00 X000b XXXX X000b XXXX X000b XXXX X000b XX00 X000b XX00 X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XX00 X000b XX00 X000b XX00 X000b X: Undefined
The blank areas are reserved. No access is allowed.
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4. Special Function Registers (SFRs)
Table 4.4 Address 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h 006Ah 006Bh 006Ch 006Dh 006Eh 006Fh 0070h 0071h 0072h 0073h 0074h 0075h 0076h 0077h 0078h 0079h 007Ah 007Bh 007Ch 007Dh 007Eh 007Fh Note: 1.
SFR Information (4) (1) Register Symbol Reset Value
DMA2 Interrupt Control Register DMA3 Interrupt Control Register CAN 1 Receive Completion Interrupt Control Register CAN 1 Transmit Completion Interrupt Control Register CAN 1 Receive FIFO Interrupt Control Register CAN 1 Transmit FIFO Interrupt Control Register UART4 Transmit Interrupt Control Register Real-Time Clock Compare Interrupt Control Register UART4 Receive Interrupt Control Register CAN0 Wakeup Interrupt Control Register UART3 Transmit Interrupt Control Register CAN0 Error Interrupt Control Register UART3 Receive Interrupt Control Register CAN 1 Wakeup Interrupt Control Register Real-Time Clock Cycle Interrupt Control Register CAN 1 Error Interrupt Control Register CAN0 Receive Completion Interrupt Control Register CAN0 Transmit Completion Interrupt Control Register CAN0 Receive FIFO Interrupt Control Register CAN0 Transmit FIFO Interrupt Control Register IC/OC Interrupt 0 Control Register IC/OC Channel 0 Interrupt Control Register IC/OC Interrupt 1 Control Register I2C-bus Interface Interrupt Control Register IC/OC Channel 1 Interrupt Control Register SCL/SDA Interrupt Control Register IC/OC Channel 2 Interrupt Control Register IC/OC Channel 3 Interrupt Control Register IC/OC Base Timer Interrupt Control Register
DM2IC DM3IC C1RIC C1TIC C1FRIC C1FTIC S4TIC RTCCIC S4RIC C0WIC S3TIC C0EIC S3RIC C1WIC RTCTIC C1EIC C0RIC C0TIC C0FRIC C0FTIC ICOC0IC ICOCH0IC ICOC1IC IICIC ICOCH1IC SCLDAIC ICOCH2IC ICOCH3IC BTIC
XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b X: Undefined
The blank areas are reserved. No access is allowed.
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Table 4.5 Address 0080h 0081h 0082h 0083h 0084h 0085h 0086h 0087h 0088h 0089h 008Ah 008Bh 008Ch 008Dh 008Eh 008Fh 0090h 0091h 0092h 0093h 0094h 0095h 0096h 0097h 0098h 0099h 009Ah 009Bh 009Ch 009Dh 009Eh 009Fh 00A0h 00A1h 00A2h 00A3h 00A4h 00A5h 00A6h 00A7h 00A8h 00A9h 00AAh 00ABh 00ACh 00ADh 00AEh 00AFh 00B0h to 015Fh Note: 1.
SFR Information (5) (1) Register E2dataFlash Address Register Symbol E2FA Reset Value 00h 00h XXh XXh
E2dataFlash Command Register
E2FI
00h XXh
E2dataFlash Data Register
E2FD
XXh XXh
E2dataFlash Mode Register E2dataFlash Control Register E2dataFlash Status Register 1
E2FM E2FC E2FS1
00h XXXX XXX0b XXXX XXX0b
E2dataFlash Status Register 0
E2FS0
0X00 XXXXb
X: Undefined The blank areas are reserved. No access is allowed.
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Table 4.6 Address 0160h 0161h 0162h 0163h 0164h 0165h 0166h 0167h 0168h 0169h 016Ah 016Bh 016Ch 016Dh 016Eh 016Fh 0170h 0171h 0172h 0173h 0174h 0175h 0176h 0177h 0178h 0179h 017Ah 017Bh 017Ch 017Dh 017Eh 017Fh Note: 1.
SFR Information (6) (1) Register LIN Wakeup Baud Rate Select Register LIN Baud Rate Prescaler 0 Register LIN Baud Rate Prescaler 1 Register LIN Self-test Control Register LIN Port Clock Control Register Symbol LWBR LBRP0 LBRP1 LSTC LPC Reset Value 00h 00h 00h 00h 00h
LIN0 Mode Register LIN0 Break Field Setting Register LIN0 Space Width Setting Register LIN0 Wakeup Setting Register LIN0 Interrupt Enable Register LIN0 Error Detection Enable Register LIN0 Control Register LIN0 Transmit Control Register LIN0 Mode Status Register LIN0 Status Register LIN0 Error Status Register LIN0 Response Field Setting Register LIN0 ID Buffer Register LIN0 Check Sum Buffer Register LIN0 Data 1 Buffer Register LIN0 Data 2 Buffer Register LIN0 Data 3 Buffer Register LIN0 Data 4 Buffer Register LIN0 Data 5 Buffer Register LIN0 Data 6 Buffer Register LIN0 Data 7 Buffer Register LIN0 Data 8 Buffer Register
L0MD L0BRK L0SPC L0WUP L0IE L0EDE L0C L0TC L0MST L0ST L0EST L0RFC L0IDB L0CB L0DB1 L0DB2 L0DB3 L0DB4 L0DB5 L0DB6 L0DB7 L0DB8
00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh X: Undefined
The blank areas are reserved. No access is allowed.
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4. Special Function Registers (SFRs)
Table 4.7 Address 0180h 0181h 0182h 0183h 0184h 0185h 0186h 0187h 0188h 0189h 018Ah 018Bh 018Ch 018Dh 018Eh 018Fh 0190h 0191h 0192h 0193h 0194h 0195h 0196h 0197h 0198h 0199h 019Ah 019Bh 019Ch 019Dh 019Eh 019Fh 01A0h 01A1h 01A2h 01A3h 01A4h 01A5h 01A6h 01A7h 01A8h 01A9h 01AAh 01ABh 01ACh 01ADh 01AEh 01AFh Note: 1.
SFR Information (7) (1) Register DMA0 Source Pointer Symbol SAR0 Reset Value XXh XXh 0Xh XXh XXh 0Xh XXh XXh
DMA0 Destination Pointer
DAR0
DMA0 Transfer Counter
TCR0
DMA0 Control Register
DM0CON
0000 0X00b
DMA1 Source Pointer
SAR1
XXh XXh 0Xh XXh XXh 0Xh XXh XXh
DMA1 Destination Pointer
DAR1
DMA1 Transfer Counter
TCR1
DMA1 Control Register
DM1CON
0000 0X00b
DMA2 Source Pointer
SAR2
XXh XXh 0Xh XXh XXh 0Xh XXh XXh
DMA2 Destination Pointer
DAR2
DMA2 Transfer Counter
TCR2
DMA2 Control Register
DM2CON
0000 0X00b
X: Undefined The blank areas are reserved. No access is allowed.
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Table 4.8 Address 01B0h 01B1h 01B2h 01B3h 01B4h 01B5h 01B6h 01B7h 01B8h 01B9h 01BAh 01BBh 01BCh 01BDh 01BEh 01BFh 01C0h 01C1h 01C2h 01C3h 01C4h 01C5h 01C6h 01C7h 01C8h 01C9h 01CAh 01CBh 01CCh 01CDh 01CEh 01CFh 01D0h 01D1h 01D2h 01D3h 01D4h 01D5h 01D6h 01D7h 01D8h 01D9h 01DAh 01DBh 01DCh 01DDh 01DEh 01DFh Note: 1.
SFR Information (8) (1) Register DMA3 Source Pointer Symbol SAR3 Reset Value XXh XXh 0Xh XXh XXh 0Xh XXh XXh
DMA3 Destination Pointer
DAR3
DMA3 Transfer Counter
TCR3
DMA3 Control Register
DM3CON
0000 0X00b
Timer B0-1 Register Timer B1-1 Register Timer B2-1 Register Pulse Period/Pulse Width Measurement Mode Function Select Register 1 Timer B Count Source Select Register 0 Timer B Count Source Select Register 1 Timer AB Division Control Register 0
TB01 TB11 TB21 PPWFS1 TBCS0 TBCS1 TCKDIVC0
XXh XXh XXh XXh XXh XXh XXXX X000b 00h X0h 0000 X000b
Timer A Count Source Select Register 0 Timer A Count Source Select Register 1 Timer A Count Source Select Register 2 16-bit Pulse Width Modulation Mode Function Select Register Timer A Waveform Output Function Select Register
TACS0 TACS1 TACS2 PWMFS TAPOFS
00h 00h X0h 0XX0 X00Xb XXX0 0000b
Timer A Output Waveform Change Enable Register Three-Phase Protect Control Register
TAOW TPRC
XXX0 X00Xb 00h
X: Undefined The blank areas are reserved. No access is allowed.
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Table 4.9
Address
SFR Information (9) (1)
Register Symbol
01E0h 01E1h 01E2h 01E3h 01E4h 01E5h 01E6h 01E7h 01E8h 01E9h 01EAh 01EBh 01ECh 01EDh 01EEh 01EFh 01F0h 01F1h 01F2h 01F3h 01F4h 01F5h 01F6h 01F7h 01F8h 01F9h 01FAh 01FBh 01FCh 01FDh 01FEh 01FFh 0200h 0201h 0202h 0203h 0204h 0205h 0206h 0207h 0208h 0209h 020Ah 020Bh 020Ch 020Dh 020Eh 020Fh Note: 1.
Timer B3-1 Register Timer B4-1 Register Timer B5-1 Register Pulse Period/Pulse Width Measurement Mode Function Select Register 2 Timer B Count Source Select Register 2 Timer B Count Source Select Register 3
TB31 TB41 TB51 PPWFS2 TBCS2 TBCS3
Reset Value XXh XXh XXh XXh XXh XXh XXXX X000b 00h X0h
Task Monitor Timer Register Task Monitor Timer Count Start Flag Task Monitor Timer Count Source Select Register Task Monitor Timer Protect Register
TMOS TMOSSR TMOSCS TMOSPR
XXh XXh XXXX XXX0b XXXX 0000b 00h
Interrupt Source Select Register 4 Interrupt Source Select Register 3 Interrupt Source Select Register 2 Interrupt Source Select Register
IFSR4A IFSR3A IFSR2A IFSR
00h 00h 00h 00h
Address Match Interrupt Enable Register Address Match Interrupt Enable Register 2
AIER AIER2
XXXX XX00b XXXX XX00b X: Undefined
The blank areas are reserved. No access is allowed.
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Table 4.10
Address
SFR Information (10) (1)
Register Symbol
0210h 0211h 0212h 0213h 0214h 0215h 0216h 0217h 0218h 0219h 021Ah 021Bh 021Ch 021Dh 021Eh 021Fh 0220h 0221h 0222h 0223h 0224h 0225h 0226h 0227h 0228h 0229h 022Ah 022Bh 022Ch 022Dh 022Eh 022Fh 0230h 0231h 0232h 0233h 0234h 0235h 0236h 0237h 0238h 0239h 023Ah 023Bh 023Ch 023Dh 023Eh 023Fh Note: 1.
Address Match Interrupt Register 0
RMAD0
Reset Value 00h 00h X0h 00h 00h X0h 00h 00h X0h 00h 00h X0h 0000 0001b (Other than user boot mode) 0010 0001b (User boot mode) 00X0 XX0Xb XXXX 0000b XXXX 0000b
Address Match Interrupt Register 1
RMAD1
Address Match Interrupt Register 2
RMAD2
Address Match Interrupt Register 3
RMAD3
Flash Memory Control Register 0 Flash Memory Control Register 1 Flash Memory Control Register 2 Flash Memory Control Register 3
FMR0 FMR1 FMR2 FMR3
Flash Memory Control Register 6
FMR6
XX0X XX00b
X: Undefined The blank areas are reserved. No access is allowed.
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4. Special Function Registers (SFRs)
Table 4.11
Address
SFR Information (11) (1)
Register Symbol
Reset Value
0240h 0241h 0242h 0243h 0244h 0245h 0246h 0247h 0248h 0249h 024Ah 024Bh 024Ch 024Dh 024Eh 024Fh 0250h 0251h 0252h 0253h 0254h 0255h 0256h 0257h 0258h 0259h 025Ah 025Bh 025Ch 025Dh 025Eh 025Fh 0260h 0261h 0262h 0263h 0264h 0265h 0266h 0267h 0268h 0269h 026Ah 026Bh 026Ch 026Dh 026Eh 026Fh
Note:
UART0 Transmit/Receive Mode Register UART0 Bit Rate Register UART0 Transmit Buffer Register UART0 Transmit/Receive Control Register 0 UART0 Transmit/Receive Control Register 1 UART0 Receive Buffer Register
U0MR U0BRG U0TB U0C0 U0C1 U0RB
00h XXh XXh XXh 0000 1000b 0000 0010b XXh XXh
UART Clock Select Register
UCLKSEL0
X0h
UART1 Transmit/Receive Mode Register UART1 Bit Rate Register UART1 Transmit Buffer Register UART1 Transmit/Receive Control Register 0 UART1 Transmit/Receive Control Register 1 UART1 Receive Buffer Register
U1MR U1BRG U1TB U1C0 U1C1 U1RB
00h XXh XXh XXh 0000 1000b 0000 0010b XXh XXh
UART2 Special Mode Register 4 UART2 Special Mode Register 3 UART2 Special Mode Register 2 UART2 Special Mode Register UART2 Transmit/Receive Mode Register UART2 Bit Rate Register UART2 Transmit Buffer Register UART2 Transmit/Receive Control Register 0 UART2 Transmit/Receive Control Register 1 UART2 Receive Buffer Register
U2SMR4 U2SMR3 U2SMR2 U2SMR U2MR U2BRG U2TB U2C0 U2C1 U2RB
00h 000X 0X0Xb X000 0000b X000 0000b 00h XXh XXh XXh 0000 1000b 0000 0010b XXh XXh X: Undefined
1.
The blank areas are reserved. No access is allowed.
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4. Special Function Registers (SFRs)
Table 4.12
Address
SFR Information (12) (1)
Register Symbol
Reset Value
0270h 0271h 0272h 0273h 0274h 0275h 0276h 0277h 0278h 0279h 027Ah 027Bh 027Ch 027Dh 027Eh 027Fh 0280h 0281h 0282h 0283h 0284h 0285h 0286h 0287h 0288h 0289h 028Ah 028Bh 028Ch 028Dh 028Eh 028Fh 0290h 0291h 0292h 0293h 0294h 0295h 0296h 0297h 0298h 0299h 029Ah 029Bh 029Ch 029Dh 029Eh 029Fh Note: 1.
UART4 Transmit/Receive Mode Register UART4 Bit Rate Register UART4 Transmit Buffer Register UART4 Transmit/Receive Control Register 0 UART4 Transmit/Receive Control Register 1 UART4 Receive Buffer Register
U4MR U4BRG U4TB U4C0 U4C1 U4RB
00h XXh XXh XXh 0000 1000b 0000 0010b XXh XXh X: Undefined
The blank areas are reserved. No access is allowed.
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4. Special Function Registers (SFRs)
Table 4.13
Address
SFR Information (13) (1)
Register Symbol
Reset Value
02A0h 02A1h 02A2h 02A3h 02A4h 02A5h 02A6h 02A7h 02A8h 02A9h 02AAh 02ABh 02ACh 02ADh 02AEh 02AFh 02B0h 02B1h 02B2h 02B3h 02B4h 02B5h 02B6h 02B7h 02B8h 02B9h 02BAh 02BBh 02BCh 02BDh 02BEh 02BFh 02C0h 02C1h 02C2h 02C3h 02C4h 02C5h 02C6h 02C7h 02C8h 02C9h 02CAh 02CBh 02CCh 02CDh 02CEh 02CFh Note: 1.
UART3 Transmit/Receive Mode Register UART3 Bit Rate Register UART3 Transmit Buffer Register UART3 Transmit/Receive Control Register 0 UART3 Transmit/Receive Control Register 1 UART3 Receive Buffer Register I2C0 Data Shift Register I2C0 Address Register 0 I2C0 Control Register 0 I2C0 Clock Control Register I2C0 Start/Stop Condition Control Register I2C0 Control Register 1 I2C0 Control Register 2 I2C0 Status Register 0 I2C0 Status Register 1 I2C0 Address Register 1 I2C0 Address Register 2
U3MR U3BRG U3TB U3C0 U3C1 U3RB S00 S0D0 S1D0 S20 S2D0 S3D0 S4D0 S10 S11 S0D1 S0D2
00h XXh XXh XXh 0000 1000b 0000 0010b XXh XXh XXh 0000 000Xb 00h 00h 0001 1010b 0011 0000b 00h 0001 000Xb XXXX X000b 0000 000Xb 0000 000Xb
Time Measurement Register 0 Waveform Generation Register 0 Time Measurement Register 1 Waveform Generation Register 1 Time Measurement Register 2 Waveform Generation Register 2 Time Measurement Register 3 Waveform Generation Register 3 Time Measurement Register 4 Waveform Generation Register 4 Time Measurement Register 5 Waveform Generation Register 5 Time Measurement Register 6 Waveform Generation Register 6 Time Measurement Register 7 Waveform Generation Register 7
G1TM0 G1PO0 G1TM1 G1PO1 G1TM2 G1PO2 G1TM3 G1PO3 G1TM4 G1PO4 G1TM5 G1PO5 G1TM6 G1PO6 G1TM7 G1PO7
XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh X: Undefined
The blank areas are reserved. No access is allowed.
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Table 4.14 Address 02D0h 02D1h 02D2h 02D3h 02D4h 02D5h 02D6h 02D7h 02D8h 02D9h 02DAh 02DBh 02DCh 02DDh 02DEh 02DFh 02E0h 02E1h 02E2h 02E3h 02E4h 02E5h 02E6h 02E7h 02E8h 02E9h 02EAh 02EBh 02ECh 02EDh 02EEh 02EFh 02F0h 02F1h 02F2h 02F3h 02F4h 02F5h 02F6h 02F7h 02F8h 02F9h 02FAh 02FBh 02FCh 02FDh 02FEh 02FFh Note: 1.
SFR Information (14) (1) Register Waveform Generation Control Register 0 Waveform Generation Control Register 1 Waveform Generation Control Register 2 Waveform Generation Control Register 3 Waveform Generation Control Register 4 Waveform Generation Control Register 5 Waveform Generation Control Register 6 Waveform Generation Control Register 7 Time Measurement Control Register 0 Time Measurement Control Register 1 Time Measurement Control Register 2 Time Measurement Control Register 3 Time Measurement Control Register 4 Time Measurement Control Register 5 Time Measurement Control Register 6 Time Measurement Control Register 7 Base Timer Register Base Timer Control Register 0 Base Timer Control Register 1 Time Measurement Prescaler Register 6 Time Measurement Prescaler Register 7 Function Enable Register Function Select Register Base Timer Reset Register Count Source Divide Register Waveform Output Master Enable Register Timer S I/O Control Register 0 Timer S I/O Control Register 1 Interrupt Request Register Interrupt Enable Register 0 Interrupt Enable Register 1 Symbol G1POCR0 G1POCR1 G1POCR2 G1POCR3 G1POCR4 G1POCR5 G1POCR6 G1POCR7 G1TMCR0 G1TMCR1 G1TMCR2 G1TMCR3 G1TMCR4 G1TMCR5 G1TMCR6 G1TMCR7 G1BT G1BCR0 G1BCR1 G1TPR6 G1TPR7 G1FE G1FS G1BTRR G1DV G1OER G1IOR0 G1IOR1 G1IR G1IE0 G1IE1 Reset Value 0X00 XX00b 0X00 XX00b 0X00 XX00b 0X00 XX00b 0X00 XX00b 0X00 XX00b 0X00 XX00b 0X00 XX00b 00h 00h 00h 00h 00h 00h 00h 00h XXh XXh 00h 00h 00h 00h 00h 00h XXh XXh 00h 00h 00h 00h XXh 00h 00h
NMI Digital Debounce Register P1_7 Digital Debounce Register
NDDR P17DDR
FFh FFh X: Undefined
The blank areas are reserved. No access is allowed.
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Table 4.15 Address 0300h 0301h 0302h 0303h 0304h 0305h 0306h 0307h 0308h 0309h 030Ah 030Bh 030Ch 030Dh 030Eh 030Fh 0310h 0311h 0312h 0313h 0314h 0315h 0316h 0317h 0318h 0319h 031Ah 031Bh 031Ch 031Dh 031Eh 031Fh 0320h 0321h 0322h 0323h 0324h 0325h 0326h 0327h 0328h 0329h 032Ah 032Bh 032Ch 032Dh 032Eh 032Fh Note: 1.
SFR Information (15) (1) Register Timer B3/B4/B5 Count Start Flag Timer A1-1 Register Timer A2-1 Register Timer A4-1 Register Three-Phase PWM Control Register 0 Three-Phase PWM Control Register 1 Three-Phase Output Buffer Register 0 Three-Phase Output Buffer Register 1 Dead Time Timer Timer B2 Interrupt Generation Frequency Set Counter Position-Data-Retain Function Control Register Timer B3 Register Timer B4 Register Timer B5 Register Symbol TBSR TA11 TA21 TA41 INVC0 INVC1 IDB0 IDB1 DTT ICTB2 PDRF TB3 TB4 TB5 Reset Value 000X XXXXb XXh XXh XXh XXh XXh XXh 00h 00h XX11 1111b XX11 1111b XXh XXh XXXX 0000b XXh XXh XXh XXh XXh XXh
Port Function Control Register
PFCR
0011 1111b
Timer B3 Mode Register Timer B4 Mode Register Timer B5 Mode Register
TB3MR TB4MR TB5MR
00XX 0000b 00XX 0000b 00XX 0000b
Count Start Flag One-Shot Start Flag Trigger Select Register Increment/Decrement Flag Timer A0 Register Timer A1 Register Timer A2 Register Timer A3 Register Timer A4 Register
TABSR ONSF TRGSR UDF TA0 TA1 TA2 TA3 TA4
00h 00h 00h 00h XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh X: Undefined
The blank areas are reserved. No access is allowed.
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4. Special Function Registers (SFRs)
Table 4.16
Address
SFR Information (16) (1)
Register Symbol
0330h 0331h 0332h 0333h 0334h 0335h 0336h 0337h 0338h 0339h 033Ah 033Bh 033Ch 033Dh 033Eh 033Fh 0340h 0341h 0342h 0343h 0344h 0345h 0346h 0347h 0348h 0349h 034Ah 034Bh 034Ch 034Dh 034Eh 034Fh 0350h 0351h 0352h 0353h 0354h 0355h 0356h 0357h 0358h 0359h 035Ah 035Bh 035Ch 035Dh 035Eh 035Fh Note: 1.
Timer B0 Register Timer B1 Register Timer B2 Register Timer A0 Mode Register Timer A1 Mode Register Timer A2 Mode Register Timer A3 Mode Register Timer A4 Mode Register Timer B0 Mode Register Timer B1 Mode Register Timer B2 Mode Register Timer B2 Special Mode Register Real-Time Clock Second Data Register Real-Time Clock Minute Data Register Real-Time Clock Hour Data Register Real-Time Clock Day Data Register Real-Time Clock Control Register 1 Real-Time Clock Control Register 2 Real-Time Clock Count Source Select Register Real-Time Clock Second Compare Data Register Real-Time Clock Minute Compare Data Register Real-Time Clock Hour Compare Data Register
TB0 TB1 TB2 TA0MR TA1MR TA2MR TA3MR TA4MR TB0MR TB1MR TB2MR TB2SC RTCSEC RTCMIN RTCHR RTCWK RTCCR1 RTCCR2 RTCCSR RTCCSEC RTCCMIN RTCCHR
Reset Value XXh XXh XXh XXh XXh XXh 00h 00h 00h 00h 00h 00XX 0000b 00XX 0000b 00XX 0000b X000 0000b 00h X000 0000b XX00 0000b XXXX X000b 0000 X00Xb X000 0000b XXX0 0000b X000 0000b X000 0000b X000 0000b
SS0 Bit Counter Register SS0 Transmit Data Register SS0 Receive Data Register SS0 Control Register H SS0 Control Register L SS0 Mode Register SS0 Enable Register SS0 Status Register SS0 Mode Register 2
SS0BR SS0TDR SS0RDR SS0CRH SS0CRL SS0MR SS0ER SS0SR SS0MR2
1111 1000b FFh FFh FFh FFh 00h 0111 1101b 0001 0000b 00h 00h 00h
X: Undefined The blank areas are reserved. No access is allowed.
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Table 4.17 Address 0360h 0361h 0362h 0363h 0364h 0365h 0366h 0367h 0368h 0369h 036Ah 036Bh 036Ch 036Dh 036Eh 036Fh 0370h 0371h 0372h 0373h 0374h 0375h 0376h 0377h 0378h 0379h 037Ah 037Bh 037Ch 037Dh 037Eh 037Fh 0380h 0381h 0382h 0383h 0384h 0385h 0386h 0387h 0388h 0389h 038Ah 038Bh 038Ch 038Dh 038Eh 038Fh
SFR Information (17) (1) Register Pull-Up Control Register 0 Pull-Up Control Register 1 Pull-Up Control Register 2 Symbol PUR0 PUR1 PUR2 Reset Value 00h 00h 00h
Port Control Register
PCR
0XX0 0XX0b
Input Threshold Select Register 0 Input Threshold Select Register 1 Input Threshold Select Register 2 Pin Assignment Control Register
VLT0 VLT1 VLT2 PACR
00h 00h XX00 0000b 0XXX X000b
Count Source Protection Mode Register Watchdog Timer Refresh Register Watchdog Timer Start Register Watchdog Timer Control Register
CSPR WDTR WDTS WDC
00h (2) XXh XXh 00XX XXXXb
X: Undefined Notes: 1. The blank areas are reserved. No access is allowed. 2. When the CSPROINI bit in the OFS1 address is 0, the reset value is 10000000b.
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4. Special Function Registers (SFRs)
Table 4.18 Address 0390h 0391h 0392h 0393h 0394h 0395h 0396h 0397h 0398h 0399h 039Ah 039Bh 039Ch 039Dh 039Eh 039Fh 03A0h 03A1h 03A2h 03A3h 03A4h 03A5h 03A6h 03A7h 03A8h 03A9h 03AAh 03ABh 03ACh 03ADh 03AEh 03AFh 03B0h 03B1h 03B2h 03B3h 03B4h 03B5h 03B6h 03B7h 03B8h 03B9h 03BAh 03BBh 03BCh 03BDh 03BEh 03BFh Note: 1.
SFR Information (18) (1) Register DMA2 Source Select Register DMA3 Source Select Register Symbol DM2SL DM3SL Reset Value 00h 00h
DMA0 Source Select Register DMA1 Source Select Register
DM0SL DM1SL
00h 00h
Open-Circuit Detection Assist Function Register
AINRST
XX00 XXXXb
SFR Snoop Address Register CRC Mode Register
CRCSAR CRCMR
XXXX XXXXb 00XX XXXXb 0XXX XXX0b
CRC Data Register CRC Input Register
CRCD CRCIN
XXh XXh XXh X: Undefined
The blank areas are reserved. No access is allowed.
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4. Special Function Registers (SFRs)
Table 4.19 Address 03C0h 03C1h 03C2h 03C3h 03C4h 03C5h 03C6h 03C7h 03C8h 03C9h 03CAh 03CBh 03CCh 03CDh 03CEh 03CFh 03D0h 03D1h 03D2h 03D3h 03D4h 03D5h 03D6h 03D7h 03D8h 03D9h 03DAh 03DBh 03DCh 03DDh 03DEh 03DFh 03E0h 03E1h 03E2h 03E3h 03E4h 03E5h 03E6h 03E7h 03E8h 03E9h 03EAh 03EBh 03ECh 03EDh 03EEh 03EFh Note: 1.
SFR Information (19) (1) Register A/D Register 0 A/D Register 1 A/D Register 2 A/D Register 3 A/D Register 4 A/D Register 5 A/D Register 6 A/D Register 7 Symbol AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 Reset Value XXXX XXXXb 0000 00XXb XXXX XXXXb 0000 00XXb XXXX XXXXb 0000 00XXb XXXX XXXXb 0000 00XXb XXXX XXXXb 0000 00XXb XXXX XXXXb 0000 00XXb XXXX XXXXb 0000 00XXb XXXX XXXXb 0000 00XXb
A/D Control Register 2 A/D Control Register 0 A/D Control Register 1 D/A0 Register
ADCON2 ADCON0 ADCON1 DA0
0000 X00Xb 0000 0XXXb 0000 X000b 00h
D/A Control Register
DACON
00h
Port P0 Register Port P1 Register Port P0 Direction Register Port P1 Direction Register Port P2 Register Port P3 Register Port P2 Direction Register Port P3 Direction Register Port P4 Register Port P5 Register Port P4 Direction Register Port P5 Direction Register Port P6 Register Port P7 Register Port P6 Direction Register Port P7 Direction Register
P0 P1 PD0 PD1 P2 P3 PD2 PD3 P4 P5 PD4 PD5 P6 P7 PD6 PD7
XXh XXh 00h 00h XXh XXh 00h 00h XXh XXh 00h 00h XXh XXh 00h 00h X: Undefined
The blank areas are reserved. No access is allowed.
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4. Special Function Registers (SFRs)
Table 4.20 Address 03F0h 03F1h 03F2h 03F3h 03F4h 03F5h 03F6h 03F7h 03F8h 03F9h 03FAh 03FBh 03FCh 03FDh 03FEh 03FFh Note: 1.
SFR Information (20) (1) Register Port P8 Register Port P9 Register Port P8 Direction Register Port P9 Direction Register Port P10 Register Port P10 Direction Register Symbol P8 P9 PD8 PD9 P10 PD10 Reset Value XXh XXh 00h 00h XXh 00h
X: Undefined The blank areas are reserved. No access is allowed.
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4. Special Function Registers (SFRs)
Table 4.21 Address D1F0h D1F1h D1F2h D1F3h D1F4h D1F5h D1F6h D1F7h D1F8h D1F9h D1FAh D1FBh D1FCh D1FDh D1FEh D1FFh D200h D201h D202h D203h D204h D205h D206h D207h D208h D209h D20Ah D20Bh D20Ch D20Dh D20Eh D20Fh D210h D211h D212h D213h D214h D215h D216h D217h D218h D219h D21Ah D21Bh D21Ch D21Dh D21Eh D21Fh Note: 1.
SFR Information (21) (1) Register Symbol Reset Value
CAN1 Mailbox 0: Message Identifier
XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh X: Undefined
CAN1 Mailbox 0: Data Length C1MB0 CAN1 Mailbox 0: Data Field
CAN1 Mailbox 0: Time Stamp
CAN1 Message Identifier
CAN1 Mailbox 1: Data Length C1MB1 CAN1 Mailbox 1: Data Field
CAN1 Mailbox 1: Time Stamp
The blank areas are reserved. No access is allowed.
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Table 4.22 Address D220h D221h D222h D223h D224h D225h D226h D227h D228h D229h D22Ah D22Bh D22Ch D22Dh D22Eh D22Fh D230h D231h D232h D233h D234h D235h D236h D237h D238h D239h D23Ah D23Bh D23Ch D23Dh D23Eh D23Fh D240h D241h D242h D243h D244h D245h D246h D247h D248h D249h D24Ah D24Bh D24Ch D24Dh D24Eh D24Fh Note: 1.
SFR Information (22) (1) Register CAN1 Mailbox 2: Message Identifier Symbol Reset Value XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh X: Undefined
CAN1 Mailbox 2: Data Length C1MB2 CAN1 Mailbox 2: Data Field
CAN1 Mailbox 2: Time Stamp
CAN1 Mailbox 3: Message Identifier
CAN1 Mailbox 3: Data Length C1MB3 CAN1 Mailbox 3: Data Field
CAN1 Mailbox 3: Time Stamp
CAN1 Mailbox 4: Message Identifier
CAN1 Mailbox 4: Data Length C1MB4 CAN1 Mailbox 4: Data Field
CAN1 Mailbox 4: Time Stamp
The blank areas are reserved. No access is allowed.
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4. Special Function Registers (SFRs)
Table 4.23 Address D250h D251h D252h D253h D254h D255h D256h D257h D258h D259h D25Ah D25Bh D25Ch D25Dh D25Eh D25Fh D260h D261h D262h D263h D264h D265h D266h D267h D268h D269h D26Ah D26Bh D26Ch D26Dh D26Eh D26Fh D270h D271h D272h D273h D274h D275h D276h D277h D278h D279h D27Ah D27Bh D27Ch D27Dh D27Eh D27Fh Note: 1.
SFR Information (23) (1) Register CAN1 Mailbox 5: Message Identifier Symbol Reset Value XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh X: Undefined
CAN1 Mailbox 5: Data Length C1MB5 CAN1 Mailbox 5: Data Field
CAN1 Mailbox 5: Time Stamp
CAN1 Mailbox 6: Message Identifier
CAN1 Mailbox 6: Data Length C1MB6 CAN1 Mailbox 6: Data Field
CAN1 Mailbox 6: Time Stamp
CAN1 Mailbox 7: Message Identifier
CAN1 Mailbox 7: Data Length C1MB7 CAN1 Mailbox 7: Data Field
CAN1 Mailbox 7: Time Stamp
The blank areas are reserved. No access is allowed.
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Table 4.24 Address D280h D281h D282h D283h D284h D285h D286h D287h D288h D289h D28Ah D28Bh D28Ch D28Dh D28Eh D28Fh D290h D291h D292h D293h D294h D295h D296h D297h D298h D299h D29Ah D29Bh D29Ch D29Dh D29Eh D29Fh D2A0h D2A1h D2A2h D2A3h D2A4h D2A5h D2A6h D2A7h D2A8h D2A9h D2AAh D2ABh D2ACh D2ADh D2AEh D2AFh Note: 1.
SFR Information (24) (1) Register CAN1 Mailbox 8: Message Identifier Symbol Reset Value XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh X: Undefined
CAN1 Mailbox 8: Data Length C1MB8 CAN1 Mailbox 8: Data Field
CAN1 Mailbox 8: Time Stamp
CAN1 Mailbox 9: Message Identifier
CAN1 Mailbox 9: Data Length C1MB9 CAN1 Mailbox 9: Data Field
CAN1 Mailbox 9: Time Stamp
CAN1 Mailbox 10: Message Identifier
CAN1 Mailbox 10: Data Length C1MB10 CAN1 Mailbox 10: Data Field
CAN1 Mailbox 10: Time Stamp
The blank areas are reserved. No access is allowed.
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Table 4.25 Address D2B0h D2B1h D2B2h D2B3h D2B4h D2B5h D2B6h D2B7h D2B8h D2B9h D2BAh D2BBh D2BCh D2BDh D2BEh D2BFh D2C0h D2C1h D2C2h D2C3h D2C4h D2C5h D2C6h D2C7h D2C8h D2C9h D2CAh D2CBh D2CCh D2CDh D2CEh D2CFh D2D0h D2D1h D2D2h D2D3h D2D4h D2D5h D2D6h D2D7h D2D8h D2D9h D2DAh D2DBh D2DCh D2DDh D2DEh D2DFh Note: 1.
SFR Information (25) (1) Register CAN1 Mailbox 11: Message Identifier Symbol Reset Value XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh X: Undefined
CAN1 Mailbox 11: Data Length C1MB11 CAN1 Mailbox 11: Data Field
CAN1 Mailbox 11: Time Stamp
CAN1 Mailbox 12: Message Identifier
CAN1 Mailbox 12: Data Length C1MB12 CAN1 Mailbox 12: Data Field
CAN1 Mailbox 12: Time Stamp
CAN1 Mailbox 13: Message Identifier
CAN1 Mailbox 13: Data Length C1MB13 CAN1 Mailbox 13: Data Field
CAN1 Mailbox 13: Time Stamp
The blank areas are reserved. No access is allowed.
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M16C/5M Group, M16C/57 Group
4. Special Function Registers (SFRs)
Table 4.26 Address D2E0h D2E1h D2E2h D2E3h D2E4h D2E5h D2E6h D2E7h D2E8h D2E9h D2EAh D2EBh D2ECh D2EDh D2EEh D2EFh D2F0h D2F1h D2F2h D2F3h D2F4h D2F5h D2F6h D2F7h D2F8h D2F9h D2FAh D2FBh D2FCh D2FDh D2FEh D2FFh D300h D301h D302h D303h D304h D305h D306h D307h D308h D309h D30Ah D30Bh D30Ch D30Dh D30Eh D30Fh Note: 1.
SFR Information (26) (1) Register CAN1 Mailbox 14: Message Identifier Symbol Reset Value XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh X: Undefined
CAN1 Mailbox 14: Data Length C1MB14 CAN1 Mailbox 14: Data Field
CAN1 Mailbox 14: Time Stamp
CAN1 Mailbox 15: Message Identifier
CAN1 Mailbox 15: Data Length C1MB15 CAN1 Mailbox 15: Data Field
CAN1 Mailbox 15: Time Stamp
CAN1 Mailbox16: Message Identifier
CAN1 Mailbox 16: Data Length C1MB16 CAN1 Mailbox 16: Data Field
CAN1 Mailbox 16: Time Stamp
The blank areas are reserved. No access is allowed.
REJ03B0267-0101 Jul 23, 2010
Rev.1.01
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M16C/5M Group, M16C/57 Group
4. Special Function Registers (SFRs)
Table 4.27 Address D310h D311h D312h D313h D314h D315h D316h D317h D318h D319h D31Ah D31Bh D31Ch D31Dh D31Eh D31Fh D320h D321h D322h D323h D324h D325h D326h D327h D328h D329h D32Ah D32Bh D32Ch D32Dh D32Eh D32Fh D330h D331h D332h D333h D334h D335h D336h D337h D338h D339h D33Ah D33Bh D33Ch D33Dh D33Eh D33Fh Note: 1.
SFR Information (27) (1) Register CAN1 Mailbox 17: Message Identifier Symbol Reset Value XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh X: Undefined
CAN1 Mailbox 17: Data Length C1MB17 CAN1 Mailbox 17: Data Field
CAN1 Mailbox 17: Time Stamp
CAN1 Mailbox 18: Message Identifier
CAN1 Mailbox 18: Data Length C1MB18 CAN1 Mailbox 18: Data Field
CAN1 Mailbox 18: Time Stamp
CAN1 Mailbox 19: Message Identifier
CAN1 Mailbox 19: Data Length C1MB19 CAN1 Mailbox 19: Data Field
CAN1 Mailbox 19: Time Stamp
The blank areas are reserved. No access is allowed.
REJ03B0267-0101 Jul 23, 2010
Rev.1.01
Page 58 of 156
M16C/5M Group, M16C/57 Group
4. Special Function Registers (SFRs)
Table 4.28 Address D340h D341h D342h D343h D344h D345h D346h D347h D348h D349h D34Ah D34Bh D34Ch D34Dh D34Eh D34Fh D350h D351h D352h D353h D354h D355h D356h D357h D358h D359h D35Ah D35Bh D35Ch D35Dh D35Eh D35Fh D360h D361h D362h D363h D364h D365h D366h D367h D368h D369h D36Ah D36Bh D36Ch D36Dh D36Eh D36Fh Note: 1.
SFR Information (28) (1) Register CAN1 Mailbox 20: Message Identifier Symbol Reset Value XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh X: Undefined
CAN1 Mailbox 20: Data Length C1MB20 CAN1 Mailbox 20: Data Field
CAN1 Mailbox 20: Time Stamp
CAN1 Mailbox 21: Message Identifier
CAN1 Mailbox 21: Data Length C1MB21 CAN1 Mailbox 21: Data Field
CAN1 Mailbox 21: Time Stamp
CAN1 Mailbox 22: Message Identifier
CAN1 Mailbox 22: Data Length C1MB22 CAN1 Mailbox 22: Data Field
CAN1 Mailbox 22: Time Stamp
The blank areas are reserved. No access is allowed.
REJ03B0267-0101 Jul 23, 2010
Rev.1.01
Page 59 of 156
M16C/5M Group, M16C/57 Group
4. Special Function Registers (SFRs)
Table 4.29 Address D370h D371h D372h D373h D374h D375h D376h D377h D378h D379h D37Ah D37Bh D37Ch D37Dh D37Eh D37Fh D380h D381h D382h D383h D384h D385h D386h D387h D388h D389h D38Ah D38Bh D38Ch D38Dh D38Eh D38Fh D390h D391h D392h D393h D394h D395h D396h D397h D398h D399h D39Ah D39Bh D39Ch D39Dh D39Eh D39Fh Note: 1.
SFR Information (29) (1) Register CAN1 Mailbox 23: Message Identifier Symbol Reset Value XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh X: Undefined
CAN1 Mailbox 23: Data Length C1MB23 CAN1 Mailbox 23: Data Field
CAN1 Mailbox 23: Time Stamp
CAN1 Mailbox 24: Message Identifier
CAN1 Mailbox 24: Data Length C1MB24 CAN1 Mailbox 24: Data Field
CAN1 Mailbox 24: Time Stamp
CAN1 Mailbox 25: Message Identifier
CAN1 Mailbox 25: Data Length C1MB25 CAN1 Mailbox 25: Data Field
CAN1 Mailbox 25: Time Stamp
The blank areas are reserved. No access is allowed.
REJ03B0267-0101 Jul 23, 2010
Rev.1.01
Page 60 of 156
M16C/5M Group, M16C/57 Group
4. Special Function Registers (SFRs)
Table 4.30 Address D3A0h D3A1h D3A2h D3A3h D3A4h D3A5h D3A6h D3A7h D3A8h D3A9h D3AAh D3ABh D3ACh D3ADh D3AEh D3AFh D3B0h D3B1h D3B2h D3B3h D3B4h D3B5h D3B6h D3B7h D3B8h D3B9h D3BAh D3BBh D3BCh D3BDh D3BEh D3BFh D3C0h D3C1h D3C2h D3C3h D3C4h D3C5h D3C6h D3C7h D3C8h D3C9h D3CAh D3CBh D3CCh D3CDh D3CEh D3CFh Note: 1.
SFR Information (30) (1) Register CAN1 Mailbox 26: Message Identifier Symbol Reset Value XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh X: Undefined
CAN1 Mailbox 26: Data Length C1MB26 CAN1 Mailbox 26: Data Field
CAN1 Mailbox 26: Time Stamp
CAN1 Mailbox 27: Message Identifier
CAN1 Mailbox 27: Data Length C1MB27 CAN1 Mailbox 27: Data Field
CAN1 Mailbox 27: Time Stamp
CAN1 Mailbox 28: Message Identifier
CAN1 Mailbox 28: Data Length C1MB28 CAN1 Mailbox 28: Data Field
CAN1 Mailbox 28: Time Stamp
The blank areas are reserved. No access is allowed.
REJ03B0267-0101 Jul 23, 2010
Rev.1.01
Page 61 of 156
M16C/5M Group, M16C/57 Group
4. Special Function Registers (SFRs)
Table 4.31 Address D3D0h D3D1h D3D2h D3D3h D3D4h D3D5h D3D6h D3D7h D3D8h D3D9h D3DAh D3DBh D3DCh D3DDh D3DEh D3DFh D3E0h D3E1h D3E2h D3E3h D3E4h D3E5h D3E6h D3E7h D3E8h D3E9h D3EAh D3EBh D3ECh D3EDh D3EEh D3EFh D3F0h D3F1h D3F2h D3F3h D3F4h D3F5h D3F6h D3F7h D3F8h D3F9h D3FAh D3FBh D3FCh D3FDh D3FEh D3FFh Note: 1.
SFR Information (31) (1) Register CAN1 Mailbox 29: Message Identifier Symbol Reset Value XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh X: Undefined
CAN1 Mailbox 29: Data Length C1MB29 CAN1 Mailbox 29: Data Field
CAN1 Mailbox 29: Time Stamp
CAN1 Mailbox 30: Message Identifier
CAN1 Mailbox 30: Data Length C1MB30 CAN1 Mailbox 30: Data Field
CAN1 Mailbox 30: Time Stamp
CAN1 Mailbox 31: Message Identifier
CAN1 Mailbox 31: Data Length C1MB31 CAN1 Mailbox 31: Data Field
CAN1 Mailbox 31: Time Stamp
The blank areas are reserved. No access is allowed.
REJ03B0267-0101 Jul 23, 2010
Rev.1.01
Page 62 of 156
M16C/5M Group, M16C/57 Group
4. Special Function Registers (SFRs)
Table 4.32 Address D400h D401h D402h D403h D404h D405h D406h D407h D408h D409h D40Ah D40Bh D40Ch D40Dh D40Eh D40Fh D410h D411h D412h D413h D414h D415h D416h D417h D418h D419h D41Ah D41Bh D41Ch D41Dh D41Eh D41Fh D420h D421h D422h D423h D424h D425h D426h D427h D428h D429h D42Ah D42Bh D42Ch D42Dh D42Eh D42Fh D430h to D49Fh Note: 1.
SFR Information (32) (1) Register CAN1 Mask Register 0 Symbol C1MKR0 Reset Value XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh
CAN1 Mask Register 1
C1MKR1
CAN1 Mask Register 2
C1MKR2
CAN1 Mask Register 3
C1MKR3
CAN1 Mask Register 4
C1MKR4
CAN1 Mask Register 5
C1MKR5
CAN1 Mask Register 6
C1MKR6
CAN1 Mask Register 7
C1MKR7
CAN1FIFO Receive ID Compare Register 0
C1FIDCR0
CAN1FIFO Receive ID Compare Register 1
C1FIDCR1
CAN1 Mask Invalid Register
C1MKIVLR
CAN1 Mailbox Interrupt Enable Register
C1MIER
X: Undefined The blank areas are reserved. No access is allowed.
REJ03B0267-0101 Jul 23, 2010
Rev.1.01
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M16C/5M Group, M16C/57 Group
4. Special Function Registers (SFRs)
Table 4.33 Address D4A0h D4A1h D4A2h D4A3h D4A4h D4A5h D4A6h D4A7h D4A8h D4A9h D4AAh D4ABh D4ACh D4ADh D4AEh D4AFh D4B0h D4B1h D4B2h D4B3h D4B4h D4B5h D4B6h D4B7h D4B8h D4B9h D4BAh D4BBh D4BCh D4BDh D4BEh D4BFh Note: 1.
SFR Information (33) (1) Register CAN1 Message Control Register 0 CAN1 Message Control Register 1 CAN1 Message Control Register 2 CAN1 Message Control Register 3 CAN1 Message Control Register 4 CAN1 Message Control Register 5 CAN1 Message Control Register 6 CAN1 Message Control Register 7 CAN1 Message Control Register 8 CAN1 Message Control Register 9 CAN1 Message Control Register 10 CAN1 Message Control Register 11 CAN1 Message Control Register 12 CAN1 Message Control Register 13 CAN1 Message Control Register 14 CAN1 Message Control Register 15 CAN1 Message Control Register 16 CAN1 Message Control Register 17 CAN1 Message Control Register 18 CAN1 Message Control Register 19 CAN1 Message Control Register 20 CAN1 Message Control Register 21 CAN1 Message Control Register 22 CAN1 Message Control Register 23 CAN1 Message Control Register 24 CAN1 Message Control Register 25 CAN1 Message Control Register 26 CAN1 Message Control Register 27 CAN1 Message Control Register 28 CAN1 Message Control Register 29 CAN1 Message Control Register 30 CAN1 Message Control Register 31 Symbol C1MCTL0 C1MCTL1 C1MCTL2 C1MCTL3 C1MCTL4 C1MCTL5 C1MCTL6 C1MCTL7 C1MCTL8 C1MCTL9 C1MCTL10 C1MCTL11 C1MCTL12 C1MCTL13 C1MCTL14 C1MCTL15 C1MCTL16 C1MCTL17 C1MCTL18 C1MCTL19 C1MCTL20 C1MCTL21 C1MCTL22 C1MCTL23 C1MCTL24 C1MCTL25 C1MCTL26 C1MCTL27 C1MCTL28 C1MCTL29 C1MCTL30 C1MCTL31 Reset Value 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h X: Undefined
The blank areas are reserved. No access is allowed.
REJ03B0267-0101 Jul 23, 2010
Rev.1.01
Page 64 of 156
M16C/5M Group, M16C/57 Group
4. Special Function Registers (SFRs)
Table 4.34 Address D4C0h D4C1h D4C2h D4C3h D4C4h D4C5h D4C6h D4C7h D4C8h D4C9h D4CAh D4CBh D4CCh D4CDh D4CEh D4CFh D4D0h D4D1h D4D2h D4D3h D4D4h D4D5h D4D6h D4D7h D4D8h D4D9h D4DAh D4DBh D4DCh D4DDh D4DEh D4DFh D4E0h to D4FFh
SFR Information (34) (1) Register CAN1 Control Register CAN1 Status Register Symbol C1CTLR C1STR Reset Value 0000 0101b 00h 0000 0101b 00h 00h CAN1 Bit Configuration Register CAN1 Clock Select Register CAN1 Receive FIFO Control Register CAN1 Receive FIFO Pointer Control Register CAN1 Transmit FIFO Control Register CAN1 Transmit FIFO Pointer Control Register CAN1 Error Interrupt Enable Register CAN1 Error Interrupt Source Judge Register CAN1 Receive Error Count Register CAN1 Transmit Error Count Register CAN1 Error Code Store Register CAN1 Channel Search Support Register CAN1 Mailbox Search Status Register CAN1 Mailbox Search Mode Register CAN1 Time Stamp Register CAN1 Acceptance Filter Support Register CAN1 Test Control Register C1BCR C1CLKR C1RFCR C1RFPCR C1TFCR C1TFPCR C1EIER C1EIFR C1RECR C1TECR C1ECSR C1CSSR C1MSSR C1MSMR C1TSR C1AFSR C1TCR 00h 00h 00h 10000000b XXh 1000 0000b XXh 00h 00h 00h 00h 00h XXh 1000 0000b XXXX XX00b 00h 00h XXh XXh 00h
X: Undefined Note: 1. The blank areas are reserved. No access is allowed.
REJ03B0267-0101 Jul 23, 2010
Rev.1.01
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M16C/5M Group, M16C/57 Group
4. Special Function Registers (SFRs)
Table 4.35 Address D500h D501h D502h D503h D504h D505h D506h D507h D508h D509h D50Ah D50Bh D50Ch D50Dh D50Eh D50Fh D510h D511h D512h D513h D514h D515h D516h D517h D518h D519h D51Ah D51Bh D51Ch D51Dh D51Eh D51Fh D520h D521h D522h D523h D524h D525h D526h D527h D528h D529h D52Ah D52Bh D52Ch D52Dh D52Eh D52Fh Note: 1.
SFR Information (35) (1) Register Symbol Reset Value XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh X: Undefined
CAN0 Mailbox 0: Message Identifier
CAN0 Mailbox 0: Data Length C0MB0
CAN0 Mailbox 0: Data Field
CAN0 Mailbox 0: Time Stamp
CAN0 Mailbox 1: Message Identifier
CAN0 Mailbox 1: Data Length
C0MB1 CAN0 Mailbox 1: Data Field
CAN0 Mailbox 1: Time Stamp
CAN0 Mailbox 2: Message Identifier
CAN0 Mailbox 2: Data Length
C0MB2 CAN0 Mailbox 2: Data Field
CAN0 Mailbox 2: Time Stamp
The blank areas are reserved. No access is allowed.
REJ03B0267-0101 Jul 23, 2010
Rev.1.01
Page 66 of 156
M16C/5M Group, M16C/57 Group
4. Special Function Registers (SFRs)
Table 4.36 Address D530h D531h D532h D533h D534h D535h D536h D537h D538h D539h D53Ah D53Bh D53Ch D53Dh D53Eh D53Fh D540h D541h D542h D543h D544h D545h D546h D547h D548h D549h D54Ah D54Bh D54Ch D54Dh D54Eh D54Fh D550h D551h D552h D553h D554h D555h D556h D557h D558h D559h D55Ah D55Bh D55Ch D55Dh D55Eh D55Fh Note: 1.
SFR Information (36) (1) Register Symbol Reset Value XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh X: Undefined
CAN0 Mailbox 3: Message Identifier
CAN0 Mailbox 3: Data Length
C0MB3 CAN0 Mailbox 3: Data Field
CAN0 Mailbox 3: Time Stamp
CAN0 Mailbox 4: Message Identifier
CAN0 Mailbox 4: Data Length
C0MB4 CAN0 Mailbox 4: Data Field
CAN0 Mailbox 4: Time Stamp
CAN0 Mailbox 5: Message Identifier
CAN0 Mailbox 5: Data Length
C0MB5 CAN0 Mailbox 5: Data Field
CAN0 Mailbox 5: Time Stamp
The blank areas are reserved. No access is allowed.
REJ03B0267-0101 Jul 23, 2010
Rev.1.01
Page 67 of 156
M16C/5M Group, M16C/57 Group
4. Special Function Registers (SFRs)
Table 4.37 Address D560h D561h D562h D563h D564h D565h D566h D567h D568h D569h D56Ah D56Bh D56Ch D56Dh D56Eh D56Fh D570h D571h D572h D573h D574h D575h D576h D577h D578h D579h D57Ah D57Bh D57Ch D57Dh D57Eh D57Fh D580h D581h D582h D583h D584h D585h D586h D587h D588h D589h D58Ah D58Bh D58Ch D58Dh D58Eh D58Fh Note: 1.
SFR Information (37) (1) Register Symbol Reset Value XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh X: Undefined
CAN0 Mailbox 6: Message Identifier
CAN0 Mailbox 6: Data Length
C0MB6 CAN0 Mailbox 6: Data Field
CAN0 Mailbox 6: Time Stamp
CAN0 Mailbox 7: Message Identifier
CAN0 Mailbox 7: Data Length C0MB7
CAN0 Mailbox 7: Data Field
CAN0 Mailbox 7: Time Stamp
CAN0 Mailbox 8: Message Identifier
CAN0 Mailbox 8: Data Length
C0MB8 CAN0 Mailbox 8: Data Field
CAN0 Mailbox 8: Time Stamp
The blank areas are reserved. No access is allowed.
REJ03B0267-0101 Jul 23, 2010
Rev.1.01
Page 68 of 156
M16C/5M Group, M16C/57 Group
4. Special Function Registers (SFRs)
Table 4.38 Address D590h D591h D592h D593h D594h D595h D596h D597h D598h D599h D59Ah D59Bh D59Ch D59Dh D59Eh D59Fh D5A0h D5A1h D5A2h D5A3h D5A4h D5A5h D5A6h D5A7h D5A8h D5A9h D5AAh D5ABh D5ACh D5ADh D5AEh D5AFh D5B0h D5B1h D5B2h D5B3h D5B4h D5B5h D5B6h D5B7h D5B8h D5B9h D5BAh D5BBh D5BCh D5BDh D5BEh D5BFh Note: 1.
SFR Information (38) (1) Register Symbol Reset Value XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh X: Undefined
CAN0 Mailbox 9: Message Identifier
CAN0 Mailbox 9: Data Length
C0MB9 CAN0 Mailbox 9: Data Field
CAN0 Mailbox 9: Time Stamp
CAN0 Mailbox 10: Message Identifier
CAN0 Mailbox 10: Data Length
C0MB10 CAN0 Mailbox 10: Data Field
CAN0 Mailbox 10: Time Stamp
CAN0 Mailbox 11: Message Identifier
CAN0 Mailbox 11: Data Length C0MB11
CAN0 Mailbox 11: Data Field
CAN0 Mailbox 11: Time Stamp
The blank areas are reserved. No access is allowed.
REJ03B0267-0101 Jul 23, 2010
Rev.1.01
Page 69 of 156
M16C/5M Group, M16C/57 Group
4. Special Function Registers (SFRs)
Table 4.39 Address D5C0h D5C1h D5C2h D5C3h D5C4h D5C5h D5C6h D5C7h D5C8h D5C9h D5CAh D5CBh D5CCh D5CDh D5CEh D5CFh D5D0h D5D1h D5D2h D5D3h D5D4h D5D5h D5D6h D5D7h D5D8h D5D9h D5DAh D5DBh D5DCh D5DDh D5DEh D5DFh D5E0h D5E1h D5E2h D5E3h D5E4h D5E5h D5E6h D5E7h D5E8h D5E9h D5EAh D5EBh D5ECh D5EDh D5EEh D5EFh Note: 1.
SFR Information (39) (1) Register Symbol Reset Value XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh X: Undefined
CAN0 Mailbox 12: Message Identifier
CAN0 Mailbox 12: Data Length C0MB12
CAN0 Mailbox 12: Data Field
CAN0 Mailbox 12: Time Stamp
CAN0 Mailbox 13: Message Identifier
CAN0 Mailbox 13: Data Length
C0MB13 CAN0 Mailbox 13: Data Field
CAN0 Mailbox 13: Time Stamp
CAN0 Mailbox 14: Message Identifier
CAN0 Mailbox 14: Data Length
C0MB14 CAN0 Mailbox 14: Data Field
CAN0 Mailbox 14: Time Stamp
The blank areas are reserved. No access is allowed.
REJ03B0267-0101 Jul 23, 2010
Rev.1.01
Page 70 of 156
M16C/5M Group, M16C/57 Group
4. Special Function Registers (SFRs)
Table 4.40 Address D5F0h D5F1h D5F2h D5F3h D5F4h D5F5h D5F6h D5F7h D5F8h D5F9h D5FAh D5FBh D5FCh D5FDh D5FEh D5FFh D600h D601h D602h D603h D604h D605h D606h D607h D608h D609h D60Ah D60Bh D60Ch D60Dh D60Eh D60Fh D610h D611h D612h D613h D614h D615h D616h D617h D618h D619h D61Ah D61Bh D61Ch D61Dh D61Eh D61Fh Note: 1.
SFR Information (40) (1) Register Symbol Reset Value XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh X: Undefined
CAN0 Mailbox 15: Message Identifier
CAN0 Mailbox 15: Data Length
C0MB15 CAN0 Mailbox 15: Data Field
CAN0 Mailbox 15: Time Stamp
CAN0 Mailbox 16: Message Identifier
CAN0 Mailbox 16: Data Length
C0MB16 CAN0 Mailbox 16: Data Field
CAN0 Mailbox 16: Time Stamp
CAN0 Mailbox 17: Message Identifier
CAN0 Mailbox 17: Data Length C0MB17
CAN0 Mailbox 17: Data Field
CAN0 Mailbox 17: Time Stamp
The blank areas are reserved. No access is allowed.
REJ03B0267-0101 Jul 23, 2010
Rev.1.01
Page 71 of 156
M16C/5M Group, M16C/57 Group
4. Special Function Registers (SFRs)
Table 4.41 Address D620h D621h D622h D623h D624h D625h D626h D627h D628h D629h D62Ah D62Bh D62Ch D62Dh D62Eh D62Fh D630h D631h D632h D633h D634h D635h D636h D637h D638h D639h D63Ah D63Bh D63Ch D63Dh D63Eh D63Fh D640h D641h D642h D643h D644h D645h D646h D647h D648h D649h D64Ah D64Bh D64Ch D64Dh D64Eh D64Fh Note: 1.
SFR Information (41) (1) Register Symbol Reset Value XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh X: Undefined
CAN0 Mailbox 18: Message Identifier
CAN0 Mailbox 18: Data Length C0MB18
CAN0 Mailbox 18: Data Field
CAN0 Mailbox 18: Time Stamp
CAN0 Mailbox 19: Message Identifier
CAN0 Mailbox 19: Data Length
C0MB19 CAN0 Mailbox 19: Data Field
CAN0 Mailbox 19: Time Stamp
CAN0 Mailbox 20: Message Identifier
CAN0 Mailbox 20: Data Length C0MB20
CAN0 Mailbox 20: Data Field
CAN0 Mailbox 20: Time Stamp
The blank areas are reserved. No access is allowed.
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Table 4.42 Address D650h D651h D652h D653h D654h D655h D656h D657h D658h D659h D65Ah D65Bh D65Ch D65Dh D65Eh D65Fh D660h D661h D662h D663h D664h D665h D666h D667h D668h D669h D66Ah D66Bh D66Ch D66Dh D66Eh D66Fh D670h D671h D672h D673h D674h D675h D676h D677h D678h D679h D67Ah D67Bh D67Ch D67Dh D67Eh D67Fh Note: 1.
SFR Information (42) (1) Register Symbol Reset Value XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh X: Undefined
CAN0 Mailbox 21: Message Identifier
CAN0 Mailbox 21: Data Length C0MB21
CAN0 Mailbox 21: Data Field
CAN0 Mailbox 21: Time Stamp
CAN0 Mailbox 22: Message Identifier
CAN0 Mailbox 22: Data Length
C0MB22 CAN0 Mailbox 22: Data Field
CAN0 Mailbox 22: Time Stamp
CAN0 Mailbox 23: Message Identifier
CAN0 Mailbox 23: Data Length C0MB23
CAN0 Mailbox 23: Data Field
CAN0 Mailbox 23: Time Stamp
The blank areas are reserved. No access is allowed.
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Table 4.43 Address D680h D681h D682h D683h D684h D685h D686h D687h D688h D689h D68Ah D68Bh D68Ch D68Dh D68Eh D68Fh D690h D691h D692h D693h D694h D695h D696h D697h D698h D699h D69Ah D69Bh D69Ch D69Dh D69Eh D69Fh D6A0h D6A1h D6A2h D6A3h D6A4h D6A5h D6A6h D6A7h D6A8h D6A9h D6AAh D6ABh D6ACh D6ADh D6AEh D6AFh Note: 1.
SFR Information (43) (1) Register Symbol Reset Value XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh X: Undefined
CAN0 Mailbox 24: Message Identifier
CAN0 Mailbox 24: Data Length
C0MB24 CAN0 Mailbox 24: Data Field
CAN0 Mailbox 24: Time Stamp
CAN0 Mailbox 25: Message Identifier
CAN0 Mailbox 25: Data Length
C0MB25 CAN0 Mailbox 25: Data Field
CAN0 Mailbox 25: Time Stamp
CAN0 Mailbox 26: Message Identifier
CAN0 Mailbox 26: Data Length
C0MB26 CAN0 Mailbox 26: Data Field
CAN0 Mailbox 26: Time Stamp
The blank areas are reserved. No access is allowed.
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Table 4.44 Address D6B0h D6B1h D6B2h D6B3h D6B4h D6B5h D6B6h D6B7h D6B8h D6B9h D6BAh D6BBh D6BCh D6BDh D6BEh D6BFh D6C0h D6C1h D6C2h D6C3h D6C4h D6C5h D6C6h D6C7h D6C8h D6C9h D6CAh D6CBh D6CCh D6CDh D6CEh D6CFh D6D0h D6D1h D6D2h D6D3h D6D4h D6D5h D6D6h D6D7h D6D8h D6D9h D6DAh D6DBh D6DCh D6DDh D6DEh D6DFh Note: 1.
SFR Information (44) (1) Register Symbol Reset Value XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh X: Undefined
CAN0 Mailbox 27: Message Identifier
CAN0 Mailbox 27: Data Length
C0MB27 CAN0 Mailbox 27: Data Field
CAN0 Mailbox 27: Time Stamp
CAN0 Mailbox 28: Message Identifier
CAN0 Mailbox 28: Data Length
C0MB28 CAN0 Mailbox 28: Data Field
CAN0 Mailbox 28: Time Stamp
CAN0 Mailbox 29: Message Identifier
CAN0 Mailbox 29: Data Length
C0MB29 CAN0 Mailbox 29: Data Field
CAN0 Mailbox 29: Time Stamp
The blank areas are reserved. No access is allowed.
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Table 4.45 Address D6E0h D6E1h D6E2h D6E3h D6E4h D6E5h D6E6h D6E7h D6E8h D6E9h D6EAh D6EBh D6ECh D6EDh D6EEh D6EFh D6F0h D6F1h D6F2h D6F3h D6F4h D6F5h D6F6h D6F7h D6F8h D6F9h D6FAh D6FBh D6FCh D6FDh D6FEh D6FFh D700h D701h D702h D703h D704h D705h D706h D707h D708h D709h D70Ah D70Bh D70Ch D70Dh D70Eh D70Fh Note: 1.
SFR Information (45) (1) Register Symbol Reset Value XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh X: Undefined
CAN0 Mailbox 30: Message Identifier
CAN0 Mailbox 30: Data Length
C0MB30 CAN0 Mailbox 30: Data Field
CAN0 Mailbox 30: Time Stamp
CAN0 Mailbox 31: Message Identifier
CAN0 Mailbox 31: Data Length C0MB31
CAN0 Mailbox 31: Data Field
CAN0 Mailbox 31: Time Stamp
CAN0 Mask Register 0
C0MKR0
CAN0 Mask Register 1
C0MKR1
CAN0 Mask Register 2
C0MKR2
CAN0 Mask Register 3
C0MKR3
The blank areas are reserved. No access is allowed.
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Table 4.46 Address D710h D711h D712h D713h D714h D715h D716h D717h D718h D719h D71Ah D71Bh D71Ch D71Dh D71Eh D71Fh D720h D721h D722h D723h D724h D725h D726h D727h D728h D729h D72Ah D72Bh D72Ch D72Dh D72Eh D72Fh D730h to D79Fh D7A0h D7A1h D7A2h D7A3h D7A4h D7A5h D7A6h D7A7h D7A8h D7A9h D7AAh D7ABh D7ACh D7ADh D7AEh D7AFh Note: 1.
SFR Information (46) (1) Register Symbol Reset Value XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh
CAN0 Mask Register 4
C0MKR4
CAN0 Mask Register 5
C0MKR5
CAN0 Mask Register 6
C0MKR6
CAN0 Mask Register 7
C0MKR7
CAN0 FIFO Receive ID Compare Register 0
C0FIDCR0
CAN0 FIFO Receive ID Compare Register 1
C0FIDCR1
CAN0 Mask Invalid Register
C0MKIVLR
CAN0 Mailbox Interrupt Enable Register
C0MIER
CAN0 Message Control Register 0 CAN0 Message Control Register 1 CAN0 Message Control Register 2 CAN0 Message Control Register 3 CAN0 Message Control Register 4 CAN0 Message Control Register 5 CAN0 Message Control Register 6 CAN0 Message Control Register 7 CAN0 Message Control Register 8 CAN0 Message Control Register 9 CAN0 Message Control Register 10 CAN0 Message Control Register 11 CAN0 Message Control Register 12 CAN0 Message Control Register 13 CAN0 Message Control Register 14 CAN0 Message Control Register 15
C0MCTL0 C0MCTL1 C0MCTL2 C0MCTL3 C0MCTL4 C0MCTL5 C0MCTL6 C0MCTL7 C0MCTL8 C0MCTL9 C0MCTL10 C0MCTL11 C0MCTL12 C0MCTL13 C0MCTL14 C0MCTL15
00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h X: Undefined
The blank areas are reserved. No access is allowed.
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Table 4.47 Address D7B0h D7B1h D7B2h D7B3h D7B4h D7B5h D7B6h D7B7h D7B8h D7B9h D7BAh D7BBh D7BCh D7BDh D7BEh D7BFh D7C0h D7C1h D7C2h D7C3h D7C4h D7C5h D7C6h D7C7h D7C8h D7C9h D7CAh D7CBh D7CCh D7CDh D7CEh D7CFh D7D0h D7D1h D7D2h D7D3h D7D4h D7D5h D7D6h D7D7h D7D8h D7D9h D7DAh D7DBh D7DCh D7DDh D7DEh D7DFh Note: 1.
SFR Information (47) (1) Register CAN0 Message Control Register 16 CAN0 Message Control Register 17 CAN0 Message Control Register 18 CAN0 Message Control Register 19 CAN0 Message Control Register 20 CAN0 Message Control Register 21 CAN0 Message Control Register 22 CAN0 Message Control Register 23 CAN0 Message Control Register 24 CAN0 Message Control Register 25 CAN0 Message Control Register 26 CAN0 Message Control Register 27 CAN0 Message Control Register 28 CAN0 Message Control Register 29 CAN0 Message Control Register 30 CAN0 Message Control Register 31 CAN0 Control Register CAN0 Status Register Symbol C0MCTL16 C0MCTL17 C0MCTL18 C0MCTL19 C0MCTL20 C0MCTL21 C0MCTL22 C0MCTL23 C0MCTL24 C0MCTL25 C0MCTL26 C0MCTL27 C0MCTL28 C0MCTL29 C0MCTL30 C0MCTL31 C0CTLR C0STR Reset Value 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 0000 0101b 00h 0000 0101b 00h 00h 00h 00h 00h 1000 0000b XXh 1000 0000b XXh 00h 00h 00h 00h 00h XXh 1000 0000b 0000 0000b 00h 00h XXh XXh 00h
CAN0 Bit Configuration Register CAN0 Clock Select Register CAN0 Receive FIFO Control Register CAN0 Receive FIFO Pointer Control Register CAN0 Transmit FIFO Control Register CAN0 Transmit FIFO pointer Control Register CAN0 Error Interrupt Enable Register CAN0 Error Interrupt Source Judge Register CAN0 Receive Error Count Register CAN0 Transmit Error Count Register CAN0 Error Code Store Register CAN0 Channel Search Support Register CAN0 Mailbox Search Status Register CAN0 Mailbox Search Mode Register CAN0 Time Stamp Register CAN0 Acceptance Filter Support Register CAN0 Test Control Register
C0BCR C0CLKR C0RFCR C0RFPCR C0TFCR C0TFPCR C0EIER C0EIFR C0RECR C0TECR C0ECSR C0CSSR C0MSSR C0MSMR C0TSR C0AFSR C0TCR
X: Undefined The blank areas are reserved. No access is allowed.
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4.2 4.2.1
Notes on SFRs Register Settings
Table 4.48 lists Registers with Write-Only Bits and registers whose function differs between reading and writing. Set these registers with immediate values. Do not use read-modify-write instructions. When establishing the next value by altering the existing value, write the existing value to the RAM as well as to the register. Transfer the next value to the register after making changes in the RAM. Read-modify-write instructions can be used when writing to the no register bits.
Table 4.48 Registers with Write-Only Bits
Address 0249h 024Bh to 024Ah 0259h 025Bh to 025Ah 0269h 026Bh to 026Ah 0299h 029Bh to 029Ah 02A9h 02ABh to 02AAh 02B6h 02B8h 0303h to 0302h 0305h to 0304h 0307h to 0306h 030Ah 030Bh 030Ch 030Dh 0327h to 0326h 0329h to 0328h 032Bh to 032Ah 032Dh to 032Ch 032Fh to 032Eh 037Dh 037Eh D4C9h D4CBh D7C9h D7CBh UART0 Bit Rate Register
Register UART0 Transmit Buffer Register UART1 Bit Rate Register UART1 Transmit Buffer Register UART2 Bit Rate Register UART2 Transmit Buffer Register UART4 Bit Rate Register UART4 Transmit Buffer Register UART3 Bit Rate Register UART3 Transmit Buffer Register I2C0 Control Register 1 I2C0 Status Register 0 Timer A1-1 Register Timer A2-1 Register Timer A4-1 Register Three-Phase Output Buffer Register 0 Three-Phase Output Buffer Register 1 Dead Time Timer Timer B2 Interrupt Generation Frequency Set Counter Timer A0 Register Timer A1 Register Timer A2 Register Timer A3 Register Timer A4 Register Watchdog Timer Refresh Register Watchdog Timer Start Register CAN1 Receive FIFO Pointer Control Register CAN1 Transmit FIFO Pointer Control Register CAN0 Receive FIFO Pointer Control Register CAN0 Transmit FIFO pointer Control Register
Symbol U0BRG U0TB U1BRG U1TB U2BRG U2TB U4BRG U4TB U3BRG U3TB S3D0 S10 TA11 TA21 TA41 IDB0 IDB1 DTT ICTB2 TA0 TA1 TA2 TA3 TA4 WDTR WDTS C1RFPCR C1TFPCR C0RFPCR C0TFPCR
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Table 4.49
Read-Modify-Write Instructions
Function Transfer Bit processing Shifting Arithmetic operation Decimal operation Logical operation Jump
Mnemonic MOVDir BCLR, BMCnd, BNOT, BSET, BTSTC, and BTSTS ROLC, RORC, ROT, SHA, and SHL ABS, ADC, ADCF, ADD, DEC, DIV, DIVU, DIVX, EXTS, INC, MUL, MULU, NEG, SBB, and SUB DADC, DADD, DSBB, and DSUB AND, NOT, OR, and XOR ADJNZ, SBJNZ
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5. Electrical Characteristics
5.
Electrical Characteristics J-Version
5.1 5.1.1
Electrical Characteristics (J-Version, Common to 3 V and 5 V) Absolute Maximum Rating
Absolute Maximum Ratings
Table 5.1
Symbol VCC AVCC VREF
Characteristic Supply voltage Analog supply voltage Analog reference voltage P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to Input voltage P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 toP9_7, P10_0 to P10_7 XIN, RESET, CNVSS, VREF P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7 XOUT
Condition VCC = AVCC VCC = AVCC
Value -0.3 to 6.5 -0.3 to 6.5
-0.3 to VCC + 0.1 (1)
Unit V V V
VI
-0.3 to VCC + 0.3
V
VO
Output voltage
-0.3 to VCC + 0.3
V
Pd
Power consumption While CPU operation Operating temperature While flash memory program and erase range operation Storage temperature range
-40C Topr 85C
300 -40 to 85
mW
Topr
Programming area Data area
0 to 60 -40 to 85 -65 to 150
C
Tstg
C
Note: 1. Maximum value is 6.5 V.
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J-Version
5.1.2
Table 5.2
Recommended Operating Conditions
Operating Conditions (1)
Value Min. 3.0 VCC 0 0 0.7 VCC VCC Typ. Max. 5.5
VCC = 3.0 V to 5.5 V, Topr = -40C to 85C unless otherwise specified. Symbol VCC AVCC VSS AVSS Supply voltage Analog supply voltage Ground voltage Analog ground voltage P0_0 to P0_7, P1_0 to P1_7, Input level 0.50 VCC P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, Input level 0.70 VCC P10_0 to P10_7 XIN, RESET, CNVSS SDAMM, SCLMM When I2C-bus input level selected Characteristic Unit V V V V V
VIH
High level input voltage
0.85VCC 0.8 VCC 0.7 VCC 2.1 0
VCC VCC VCC VCC 0.3 VCC
V
V V V
When SMBUS input level selected
VIL
P0_0 to P0_7, P1_0 to P1_7, Input level 0.50 VCC P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, Input level 0.70 VCC Low level input P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7 voltage XIN, RESET, CNVSS SDAMM, SCLMM When I2C-bus input level selected When SMBUS input level selected
0
0.45VCC
V
0 0 0
0.2 VCC 0.3 VCC 0.8 -80.0
V V V
Sum of IOH(peak) at P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 IOH(sum) High peak to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, output current P8_0 to P8_4, P8_6 to P8_7, P9_0 to P9_7, P10_0 to P10_7 High level IOH(peak) peak output current IOH(avg) P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6 to P8_7, P9_0 to P9_7, P10_0 to P10_7
mA
-10.0
mA
High level P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to average output P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6 to P8_7, P9_0 to P9_7, P10_0 to P10_7 current (1) Sum of IOL(peak) at P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 Low peak to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, output current P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to Low level peak P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, output current P9_0 to P9_7, P10_0 to P10_7 Low level P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to average output P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7 current (1) Main clock input oscillation frequency (2) Sub clock oscillation oscillator frequency PLL clock oscillation frequency (2) CPU operation frequency Wait time to stabilize PLL frequency synthesizer 10 0 0 32.768
-5.0
mA
IOL(sum)
80.0
mA
IOL(peak)
10.0
mA
IOL(avg) f(XIN) f(XCIN) f(PLL) f(BCLK) tsu(PLL)
5.0 20 50 32 32 1
mA MHz kHz MHz MHz ms
Notes: 1. The mean output current is the mean value within 100ms. 2. Refer to Figure 5.1 "Main clock input oscillation frequency, PLL clock oscillation frequency" for the relationship between main clock oscillation frequency/PLL clock oscillation frequency and supply voltage.
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J-Version
Main clock input oscillation frequency
f(XIN) maximum operating frequency [MHz] f(XIN) maximum operating frequency [MHz]
PLL clock oscillation frequency
32.0
20.0 MHz 20.0
32.0 MHz
10.0
10.0
0.0 3.0 5.5
0.0 3.0 5.5
Vcc [V] (main clock: no division)
Vcc [V] (PLL clock oscillation)
Figure 5.1
Main clock input oscillation frequency, PLL clock oscillation frequency
Table 5.3
Recommended Operating Conditions (2/2) (1)
VCC = 3.0 to 5.5 V, VSS = 0 V, and Topr = -40C to 85C unless otherwise specified. The ripple voltage must not exceed Vr(VCC) and/or dVr(VCC)/dt. Symbol Vr(VCC) dVr(VCC)/dt Allowable ripple voltage Parameter VCC = 5.0 V VCC = 3.0 V VCC = 5.0 V VCC = 3.0 V Standard Min. Typ. Max. 0.5 0.3 0.3 0.3 Unit Vp-p Vp-p V/ms V/ms
Ripple voltage falling gradient
Note: 1. The device is operationally guaranteed under these operating conditions.
VCC
Vr( VCC )
Figure 5.2
Ripple Waveform
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5.1.3 A/D Conversion Characteristics
Table 5.4 A/D Conversion Characteristics (1) VCC = AVCC = VREF = 3.0 to 5.5 V, VSS = AVSS = 0 V at Topr = -40C to 85C unless otherwise specified.
Symbol --- INL Resolution Integral Non-Linearity Error Parameter Measuring Condition VREF = VCC VREF = VCC = 5.0 V (2) VREF = VCC = 3.3 V Absolute Accuracy
(2)
Standard Min. Typ. Max. 10 3 5 3 5 2 2 2 3 25 16 10
Unit Bits LSB LSB LSB LSB MHz MHz MHz k
---
VREF = VCC = 5.0 V (2) VREF = VCC = 3.3 V (2) 4.0 V VCC 5.5 V 3.2 V VCC 4.0 V 3.0 V VCC 3.2 V
AD
A/D operating clock frequency
--- DNL --- --- tCONV tSAMP VREF VIA
Tolerance Level Impedance Differential Non-Linearity Error Offset Error Gain Error 10-bit Conversion Time Sampling time Reference Voltage Analog Input Voltage
(3) (2) (2) (2)
1 3 3 1.60 0.6 3.0 0 VCC VREF
LSB LSB LSB s s V V
VREF = VCC = 5V, AD = 25 MHz
Notes: 1. Use when AVCC = VCC 2. Flash memory rewrite disabled. Except for the analog input pin, set the pins to be measured as input ports and connect them to VSS. See Figure 5.3 "A/D Accuracy Measure Circuit". 3. When analog input voltage is over reference voltage, the result of A/D conversion is 3FFh.
AN
Analog input
P0 to P10
AN: One of the analog input pin P0 to P10: I/O pins other than AN
Figure 5.3
A/D Accuracy Measure Circuit
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J-Version
5.1.4 D/A Conversion Characteristics
Table 5.5 D/A Conversion Characteristics VCC = AVCC = VREF = 3.0 to 5.5 V, VSS = AVSS = 0 V at Topr = -40C to 85C unless otherwise specified.
Standard Min. Typ. Max. 8 2.5 3 5 See Notes 1 and 2 6 8.2 1.5
Symbol tSU RO IVREF Resolution
Parameter
Measuring Condition
Unit Bits LSB s k mA
Absolute Accuracy Setup Time Output Resistance Reference Power Supply Input Current
Notes: 1. This applies when using one D/A converter, with the D/A register for the unused D/A converter set to 00h. 2. The current consumption of the A/D converter is not included. Also, the IVREF of the D/A converter will flow even if the ADSTBY bit in the ADCON1 register is 0 (A/D operation stopped (standby)).
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5.1.5 Flash Memory Electrical Characteristics
Table 5.6 CPU Clock When Operating Flash Memory (f(BCLK)) VCC = 3.0 to 5.5 V at Topr = -40C to 85C, unless otherwise specified.
Symbol f(SLOW_R) Parameter CPU rewrite mode Slow read mode Low current consumption read mode Data flash read fC Conditions Standard Min. Typ. Max. 16 (1) 5 35 20
(3)
Unit MHz MHz kHz MHz
(2)
Notes: 1. Set the PM17 bit in the PM1 register to 1 (one wait). 2. When the frequency is over this value, set the FMR17 bit in the FMR1 register to 0 (one wait) or the PM17 bit in the PM1 register to 1 (one wait) 3. Set the PM17 bit in the PM1 register to 1 (one wait). When using the 125 kHz on-chip oscillator clock or sub clock as the CPU clock source, a wait is not necessary.
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J-Version
Table 5.7 Flash Memory (Program ROM 1, 2) Electrical Characteristics VCC = 3.0 to 5.5 V at Topr = 0C to 60C, unless otherwise specified.
Symbol td(SR-SUS) tPS Parameter Program/erase cycles (1, 3, 4) Two words program time Lock bit program time Block erase time Time delay from suspend request until suspend Interval from erase start/restart until following suspend request Suspend interval necessary for auto-erasure to complete (7) Time from suspend until erase restart Program, erase voltage Read voltage Program, erase temperature Flash Memory Circuit Stabilization Wait Time Data hold time (6) Ambient temperature = 55C 20 Topr = -40C to 85C 3.0 3.0 0 0 20 130 + --------------f ( BCLK ) 5.5 5.5 60 50 Conditions VCC = 3.3 V, Topr = 25C VCC = 3.3 V, Topr = 25C VCC = 3.3 V, Topr = 25C VCC = 3.3 V, Topr = 25C Standard Min. 1,000 (2) 150 70 0.2 4000 3000 3.0 35 + --------------f ( BCLK ) Typ. Max. Unit times s s s ms s ms s V V C s year
Notes: 1. Definition of program and erase cycles: The program and erase cycles refer to the number of per-block erasures. If the program and erase cycles are n (n = 1,000), each block can be erased n times. For example, if a 64 Kbyte block is erased after writing two word data 16,384 times, each to a different address, this counts as one program and erase cycles. Data cannot be written to the same address more than once without erasing the block (rewrite prohibited). 2. Cycles to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed). 3. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential addresses in turn so that as much of the block as possible is used up before performing an erase operation. It is advisable to retain data on the erasure cycles of each block and limit the number of erase operations to a certain number. 4. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase command at least three times until the erase error does not occur. 5. Customers desiring program/erase failure rate information should contact a Renesas Electronics sales office. 6. The data hold time includes time that the power supply is off or the clock is not supplied. 7. After an erase start or erase restart, if an interval of at least 20 ms is not set before the next suspend request, the erase sequence cannot be completed.
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J-Version
Table 5.8 Flash Memory (Data Flash) Electrical Characteristics VCC = 3.0 to 5.5 V at Topr = -40C to 85C, unless otherwise specified.
Symbol td(SR-SUS) tPS 1. Parameter Program/erase cycles (1, 3, 4) Two words program time Lock bit program time Block erase time Time delay from suspend request until suspend Interval from erase start/restart until following suspend request Suspend interval necessary for auto-erasure to complete (7) Time from suspend until erase restart Program, erase voltage Read voltage Program, erase temperature Flash memory circuit stabilization wait time Data hold time (6) Ambient temperature = 55C 20 3.0 3.0 -40 0 20 130 + --------------f ( BCLK ) 5.5 5.5 85 50 Conditions VCC = 3.3 V, Topr = 25C VCC = 3.3 V, Topr = 25C VCC = 3.3 V, Topr = 25C VCC = 3.3 V, Topr = 25C Standard Min. 10,000 (2) 300 140 0.2 4000 3000 3.0 35 + --------------f ( BCLK ) Typ. Max. Unit times s s s ms s ms s V V C s year
2. 3.
4. 5. 6. 7.
Definition of program and erase cycles The program and erase cycles refer to the number of per-block erasures. If the program and erase cycles are n (n = 10,000), each block can be erased n times. For example, if a 4 Kbyte block is erased after writing two word data 1,024 times, each to a different address, this counts as one program and erase cycles. Data cannot be written to the same address more than once without erasing the block (rewrite prohibited). Cycles to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed). In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example, when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 256 groups before erasing them all in one operation. In addition, averaging the erasure cycles between blocks A and B can further reduce the actual erasure cycles. It is also advisable to retain data on the erasure cycles of each block and limit the number of erase operations to a certain number. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase command at least three times until the erase error does not occur. Customers desiring program/erase failure rate information should contact a Renesas Electronics sales office. The data hold time includes time that the power supply is off or the clock is not supplied. After an erase start or erase restart, if an interval of at least 20 ms is not set before the next suspend request, the erase sequence cannot be completed.
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J-Version
5.1.6 E2PROM Emulation Data Flash
Table 5.9 E2PROM Emulation Data Flash Electrical Characteristics VCC = 3.0 to 5.5 V, VSS = 0 V, and Topr = -40C to 85C unless otherwise specified.
Symbol -- -- -- -- tPS -- Program/erase cycles (1) Word program time (2-byte program) Read time (2-byte read) Block erase time (32-byte block) Flash memory circuit stabilization wait time (sleep mode to normal mode) Data hold time (2) Ambient temperature = 55C (3, 4) 20 15 Characteristic Value Min. 100000 100 2000 1 200 50 Typ. Max. Unit times s s ms s years
Notes: 1. Definition of program/erase cycles definition This value represents the number of erasure per block. If the flash memory is programmed/erased n times, each block can be erased n times. i.e. If a word write is performed in different 16 addresses in a block and then the block is erased, it is considered the programming/erasure is performed just once. However a write in the same address more than once for one erasure is disabled. (overwrite disabled). 2. The data hold time includes the periods when the supply voltage is not applied and no clock is provided. 3. This data hold time includes (7000) hours in Ambient temperature = 85C. 4. Please contact a Renesas Electronics sales office regarding data retention time other than the above.
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J-Version
5.1.7 Voltage Detector and Power Supply Circuit Electrical Characteristics
Table 5.10 Voltage Detector 0 Electrical Characteristics The measurement condition is VCC = 3.0 to 5.5 V, Topr = -40C to 85C, unless otherwise specified.
Symbol Vdet0 td(E-A) Parameter Voltage detection level Vdet0 Waiting time until voltage detector operation starts (1) Condition When VCC is falling. VCC = 3.0 to 5.0 V Standard Min. 2.70 Typ. 2.85 Max. 3.00 100 Unit V s
Note:
1. Necessary time until the voltage detector operates when setting to 1 again after setting the VC25 bit in the VCR2 register to 0.
Table 5.11 Voltage Detector 2 Electrical Characteristics The measurement condition is VCC = 3.0 to 5.5 V, Topr = -40C to 85C, unless otherwise specified.
Symbol Vdet2_0 Vdet2_1 Vdet2_2 Vdet2_3 Vdet2_4 Vdet2_5 Vdet2_6 Vdet2_7 td(E-A) Parameter Voltage detection level Vdet2_0 Voltage detection level Vdet2_1 Voltage detection level Vdet2_2 Voltage detection level Vdet2_3 Voltage detection level Vdet2_4 Voltage detection level Vdet2_5 Voltage detection level Vdet2_6 Voltage detection level Vdet2_7 Hysteresis width at the rising of VCC in voltage detector 2 Waiting time until voltage detector operation starts (1) VCC = 3.0 to 5.0 V When VCC is falling 3.51 Condition Standard Min. Typ. 3.21 3.36 3.51 3.66 3.81 3.96 4.10 4.25 0.15 100 4.11 Max. Unit V V V V V V V V V s
Note:
1. Necessary time until the voltage detector operates after setting to 1 again after setting the VC27 bit in the VCR2 register to 0.
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J-Version
Table 5.12 Power-On Reset Circuit The measurement condition is Topr = -40C to 85C, unless otherwise specified.
Symbol trth tfth Vpor tw(por) Parameter External power VCC rise gradient External power VCC fall gradient Voltage at which power-on reset enabled
(1)
Condition
Standard Min. 2.0 Typ. Max.
Unit
50000 mV/ms 50000 mV/ms 0.1 V ms
Hold time at which power-on reset enabled
1.0
Note: 1. To use the power-on reset function, enable voltage monitor 0 reset by setting the LVDAS bit in the OFS1 address to 0.
Vdet0 External Power VCC Vpor tw(por) t rth t fth t rth
Vdet0
Internal reset signal 1 fOCO-S 1 fOCO-S
x 128
x 128
Figure 5.4
Power-On Reset Circuit Electrical Characteristics
Table 5.13
Symbol td(P-R) td(R-S) td(W-S)
Power Supply Circuit Timing Characteristics
Parameter Time for Internal Power Supply Stabilization During Powering-On STOP Release Time Low Power Mode Wait Mode Release Time VCC = 3.0 V to 5.5V Measuring Condition Standard Min. Typ. Max. 5 300 300 Unit ms s s
Note: 1. When VCC = 5 V.
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J-Version
Recommended operating voltage
Time to stabilize internal supply voltage during powering-on
t d(P-R)
VCC
td(P-R) CPU clock
t d(R-S)
(a) Interrupt to exit from stop mode (b) Interrupt to exit from wait mode
STOP release time
Low power consumption mode wait mode exit time
t d(W-S)
CPU clock (a) (b) td(R-S) td(W-S)
t d(E-A)
Voltage detection circuit operation start time
VC25, VC27
Voltage detection circuit
Stop td(E-A)
Operate
Figure 5.5
Power Supply Circuit Timing Diagram
5.1.8
Oscillation Circuit Electrical Characteristics
Table 5.14 On-chip Oscillator Oscillation Circuit Electrical Characteristics VCC = 3.0 to 5.5 V, Topr = -40C to 85C, unless otherwise specified
Symbol fOCO-S fOCO40M Characteristic 125 kHz on-chip oscillator oscillation frequency 40 MHz on-chip oscillator oscillation frequency Value Min. 100 32 Typ. 125 40 Max. 150 48 kHz MHz Unit
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5.2 5.2.1
Electrical Characteristics (J-Version, VCC = 5 V) Electrical Characteristics
J-Version, VCC = 5 V
Table 5.15 Electrical Characteristics (1)
Standard Min. Typ. Max.
VCC = 4.2 to 5.5 V, VSS = 0 V at Topr = -40C to 85C, f(BCLK) = 32 MHz unless otherwise specified.
Symbol Parameter P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6 to P8_7, P9_0 to P9_7, P10_0 to P10_7 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6 to P8_7,P9_0 to P9_7, P10_0 to P10_7 HIGH POWER HIGH Output Voltage VOH HIGH Output Voltage XCOUT XOUT LOW POWER HIGH POWER LOW POWER Measuring Condition Unit
VOH
HIGH Output Voltage
IOH=-5 mA
VCC-2.0
VCC
V
VOH
HIGH Output Voltage
IOH = -200 A IOH = -1 mA IOH = -0.5 mA With no load applied With no load applied
VCC--0.3 VCC--2.0 VCC--2.0 2.5 1.6
VCC
V
VCC VCC
V
V
VOL
LOW Output Voltage
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7 HIGH POWER XOUT LOW POWER HIGH POWER LOW POWER
IOL = 5 mA
2.0
V
VOL
LOW Output Voltage
IOL = 200 A
0.45
V
LOW Output Voltage VOL LOW Output Voltage
IOL = 1 mA IOL = 0.5 mA With no load applied With no load applied 0 0
2.0 V 2.0 V
XCOUT
VT+-VT-
Hysteresis
TA0IN to TA4IN, TB0IN to TB5IN, INT0 to INT7, NMI, ADTRG, CTS0 to CTS3, SCL2, SDA2, CLK0 to CLK4, TA0OUT to TA4OUT, KI0 to KI3, RXD0 to RXD4, ZP, IDU, IDW, IDV, SD, INPC1_0 to INPC1_7, SSI0, SSCK0, SCS0, LIN0IN, CRX0, CRX1
RESET
0.2
0.4VCC
V
VT+-VTVT+-VT-
Hysteresis Hysteresis
0.2 0.2
2.5 0.8
V V
XIN
IIH
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, HIGH Input Current P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7 XIN, RESET, CNVSS P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7 XIN, RESET, CNVSS P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6 to P8_7, P9_0 to P9_7, P10_0 to P10_7
VI = 5 V
5.0
A
IIL
LOW Input Current
VI = 0 V
-5.0
A
RPULLUP
Pull-Up Resistance
VI = 0 V
30
50
170
k
RfXIN RfXCIN VRAM
Feedback Resistance XIN Feedback Resistance XCIN RAM Retention Voltage At stop mode 2.0
1.5 15
M M V
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J-Version, VCC = 5 V
Table 5.16 Electrical Characteristics (2) Topr = -40C to 85C unless otherwise specified.
Symbol Parameter Measuring Condition
f(BCLK) = 32 MHz, XIN = 8 MHz (square wave), PLL multiply-by-8 125 kHz on-chip oscillator operates High speed mode f(BCLK) = 20 MHz, XIN = 20 MHz (square wave), 125 kHz on-chip oscillator operates f(BCLK) = 16 MHz, XIN = 16 MHz (square wave), 125 kHz on-chip oscillator operates Main clock stops 40 MHz on-chip oscillator operates 125 kHz on-chip oscillator operates 40 MHz on-chip oscillator No division mode Main clock stops 40 MHz on-chip oscillator operates 125 kHz on-chip oscillator operates Divide-by-8 Power Supply Current (VCC = 4.2V to 5.5 125 kHz on-chip oscillator mode V) In single-chip mode, the output pins are open and other pins are Low power mode VSS Main clock stops 40 MHz on-chip oscillator stops 125 kHz on-chip oscillator operates Divide-by-8 FMR22 = FMR23 = 1 (Low-current consumption read mode) f(BCLK) = 32 kHz On Flash memory (2) FMR22 = FMR23 = 1 (Low-current consumption read mode) Main clock stops 40 MHz on-chip oscillator stops 125 kHz on-chip oscillator operates Peripheral clock operates Topr = 25C Main clock stops 40 MHz on-chip oscillator stops 125 kHz on-chip oscillator operates Peripheral clock operates Topr = 85C Topr = 25C Topr = 85C f(BCLK) = 10 MHz, PM17 = 1 (one wait) VCC = 5.0 V f(BCLK) = 10 MHz, PM17 = 1 (one wait) VCC = 5.0 V 200
A
Standard Min. Typ.
25
Max.
45
Unit
mA
21
39
mA
17
mA
21
39
mA
6
mA
190
580
A
ICC
25
A
Wait mode
55
A
3 30 20.0 30.0 3 6
15
A A
Stop mode
During flash memory program During flash memory erase Idet2 Idet0 Low Voltage Detection Dissipation Current Reset Area Detection Dissipation Current
mA mA
A A
Note: 1. This indicates the memory in which the program to be executed exists.
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J-Version, VCC = 5 V
5.2.2 Timing Requirements (Peripheral Functions and Others)
(VCC = 5 V, VSS = 0 V, at Topr = -40C to 85C unless otherwise specified)
5.2.2.1
Table 5.17
Symbol tw(RSTL)
Reset Input (RESET Input)
Reset Input (RESET Input)
Parameter
RESET input low pulse width
Standard Min. 10 Max.
Unit
s
RESET input t w(RTSL)
Figure 5.6
Reset Input (RESET Input)
5.2.2.2
Table 5.18
Symbol tc tw(H) tw(L) tr tf
External Clock Input
External Clock Input (XIN Input) (1)
Parameter External clock input cycle time External clock input high pulse width External clock input low pulse width External clock rise time External clock fall time Standard Min. Max. 50 20 20 9 9 Unit ns ns ns ns ns
Note: 1. The condition is VCC = 5.0V.
XIN input tr t w(H) tf tc t w(L)
Figure 5.7
External Clock Input (XIN Input)
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J-Version, VCC = 5 V
Timing Requirements (VCC = 5 V, VSS = 0 V, at Topr = -40C to 85C unless otherwise specified)
5.2.2.3
Table 5.19
Symbol tc(TA) tw(TAH) tw(TAL)
Timer A Input
Timer A Input (Counter Input in Event Counter Mode)
Parameter TAiIN input cycle time TAiIN input high pulse width TAiIN input low pulse width Standard Min. Max. 100 40 40 Unit ns ns ns
Table 5.20
Symbol tc(TA) tw(TAH) tw(TAL)
Timer A Input (Gating Input in Timer Mode)
Parameter TAiIN input cycle time TAiIN input high pulse width TAiIN input low pulse width Standard Min. Max. 400 200 200 Unit ns ns ns
Table 5.21
Symbol tc(TA) tw(TAH) tw(TAL)
Timer A Input (External Trigger Input in One-shot Timer Mode)
Parameter TAiIN input cycle time TAiIN input high pulse width TAiIN input low pulse width Standard Min. Max. 200 100 100 Unit ns ns ns
Table 5.22
Symbol tw(TAH) tw(TAL)
Timer A Input (External Trigger Input in PWM Mode, Programmable Output Mode)
Parameter TAiIN input high pulse width TAiIN input low pulse width Standard Min. Max. 100 100 Unit ns ns
tc(TA) t w(TAH) TAiIN input t w(TAL) tc(UP) t w(UPH) TAiOUT input t w(UPL)
Figure 5.8
Timer A Input
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J-Version, VCC = 5 V
Timing Requirements (VCC = 5 V, VSS = 0 V, at Topr = -40C to 85C unless otherwise specified) Table 5.23
Symbol tc(TA) tsu(TAIN-TAOUT) tsu(TAOUT-TAIN) TAiIN input cycle time TAiOUT input setup time TAiIN input setup time
Timer A Input (Two-phase Pulse Input in Event Counter Mode)
Parameter Standard Min. Max. 800 200 200 Unit ns ns ns
Two-phase pulse input in event counter mode tc(TA) TAiIN input tsu(TAIN-TAOUT) TAiOUT input tsu(TAOUT-TAIN) tsu(TAIN-TAOUT) tsu(TAOUT-TAIN)
Figure 5.9
Timer A Input (Two-Phase Pulse Input in Event Counter Mode)
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J-Version, VCC = 5 V
Timing Requirements (VCC = 5 V, VSS = 0 V, at Topr = -40C to 85C unless otherwise specified)
5.2.2.4
Table 5.24
Symbol tc(TB) tw(TBH) tw(TBL) tc(TB) tw(TBH) tw(TBL)
Timer B Input
Timer B Input (Counter Input in Event Counter Mode)
Parameter TBiIN input cycle time (counted on one edge) TBiIN input high pulse width (counted on one edge) TBiIN input low pulse width (counted on one edge) TBiIN input cycle time (counted on both edges) TBiIN input high pulse width (counted on both edges) TBiIN Input low pulse width (counted on both edges) Standard Min. 100 40 40 200 80 80 Max. Unit ns ns ns ns ns ns
Table 5.25
Symbol tc(TB) tw(TBH) tw(TBL)
Timer B Input (Pulse Period Measurement Mode)
Parameter TBiIN input cycle time TBiIN input high pulse width TBiIN input low pulse width Standard Min. 400 200 200 Max. Unit ns ns ns
Table 5.26
Symbol tc(TB) tw(TBH) tw(TBL)
Timer B Input (Pulse Width Measurement Mode)
Parameter TBiIN input cycle time TBiIN input high pulse width TBiIN input low pulse width Standard Min. 400 200 200 Max. Unit ns ns ns
tc(TB) t w(TBH) TBiIN input t w(TBL)
Figure 5.10
Timer B Input
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J-Version, VCC = 5 V
Timing Requirements (VCC = 5 V, VSS = 0 V, at Topr = -40C to 85C unless otherwise specified)
5.2.2.5
Table 5.27
Symbol tw(TSH) tw(TSL) tsu(TSUDA-TSUDB) tsu(TSUDB-TSUDA)
Timer S Input
Timer S Input (Two-phase Pulse Input in Two-phase Pulse Signal Processing Mode)
Parameter TSUDA, TSUDB input high pulse width TSUDA, TSUDB input low pulse width TSUDB input setup time TSUDA input setup time Standard Min. Max. 2 2 1 1 Unit s s s s
Two-phase pulse input in two-phase pulse signal processing mode
tw(TSH) tw(TSL)
TSUDA input
tsu(TSUDA-TSUDB) tw(TSH) tsu(TSUDA-TSUDB) tsu(TSUDB-TSUDA) tw(TSL)
TSUDB input
tsu(TSUDB-TSUDA)
Note: 1. When the TSUDA and TSUDB phases are interchanged, tsu(TSUDA-TSUDB) and tsu(TSUDB-TSUDA) are also interchanged.
Figure 5.11
Timer S Input (Two-phase Pulse Input in Two-phase Pulse Signal Processing Mode)
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J-Version, VCC = 5 V
Timing Requirements (VCC = 5 V, VSS = 0 V, at Topr = -40C to 85C unless otherwise specified)
5.2.2.6
Table 5.28
Symbol tc(CK) tw(CKH) tw(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D)
Serial Interface
Serial Interface
Parameter CLKi input cycle time CLKi input high pulse width CLKi input low pulse width TXDi output delay time TXDi hold time RXDi input setup time RXDi input hold time 0 70 90 Standard Min. 200 100 100 80 Max. Unit ns ns ns ns ns ns ns
tc(CK) t w(CKH) CLKi t w(CKL) th(C-Q) TXDi td(C-Q) RXDi tsu(D-C) th(C-D)
Figure 5.12
Serial Interface
5.2.2.7
Table 5.29
Symbol tw(INH) tw(INL)
External Interrupt INTi Input
External Interrupt INTi Input
Parameter
INTi input high pulse width INTi input low pulse width
Standard Min. 250 250 Max.
Unit ns ns
t w(INL) INTi input t w(INH)
Figure 5.13
External Interrupt INTi Input
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5. Electrical Characteristics
J-Version, VCC = 5 V
Timing Requirements (VCC = 5 V, VSS = 0 V, at Topr = -40C to 85C unless otherwise specified)
5.2.2.8
Table 5.30
Symbol tBUF tHD;STA tLOW tR tHD;DAT tHIGH fF tsu;DAT tsu;STA tsu;STO
Multi-master I2C-bus
Multi-master I2C-bus
Parameter Bus free time Hold time in start condition Hold time in SCL clock 0 status SCL, SDA signals' rising time Data hold time Hold time in SCL clock 1 status SCL, SDA signals' falling time Data setup time Setup time in restart condition Stop condition setup time 250 4.7 4.0 0 4.0 300 Standard Clock Mode Min. 4.7 4.0 4.7 1000 Max. High-speed Clock Mode Min. 1.3 0.6 1.3 20 + 0.1 Cb 0 0.6 20 + 0.1 Cb 100 0.6 0.6 300 300 0.9 Max. Unit
s s s
ns
s s
ns ns
s s
SDA
t BUF t HD;STA t LOW
s
t su;STO
tR
tF
SCL
p
Sr
p
t HD;STA
t HD;DTA
t HIGH
t su;DTA
t su;STA
Figure 5.14
Multi-master I2C-bus
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5. Electrical Characteristics
J-Version, VCC = 5 V
Timing Requirements (VCC = 5 V, VSS = 0 V, at Topr = -40C to 85C unless otherwise specified)
5.2.2.9
Table 5.31
Symbol tc(SSCK) tw(SSCKH) tw(SSCKL) tr(SSCK)
Serial bus interface
Serial Bus Interface
Characteristic SSCK clock cycle time SSCK clock high pulse width SSCK clock low pulse width Master SSCK clock rising time Slave Master SSCK clock falling time Slave 100 1 Slave Slave 1 tCYC + 50 (1) 1 tCYC + 50 (1) 1 3.0 V VCC 5.5 V 3.0 V VCC 5.5 V 1.5 tCYC + 100 (1) 1.5 tCYC + 100 (1) 1 1 1 Measurement condition Value Min. 250 0.4 0.4 0.6 0.6 1 Typ. Max. Unit ns tc(SSCK) tc(SSCK) tCYC (1)
s
tf(SSCK)
tCYC (1)
s
tsu(SSIO-SSCK) SSO, SSI data input setup time th(SSCK-SSIO) SSO, SSI data input hold time
ns tCYC (1) ns ns tCYC (1) ns ns
tsu(SCS-SSCK) SCS setup time th(SSCK-SCS) td(SSCK-SSIO) ten(SCS-SSI) tdis(SCS-SSI) Note: 1.
SCS hold time
SS0, SSI data output delay time SSI output enable time SSI output disable time
1 tCYC is 1/f1 (s).
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5. Electrical Characteristics
J-Version, VCC = 5 V
4-Wire Bus Communication Mode, Master, CPHS = 1
VIH or VOH
SCS (output)
VIL or VOL t w(SSCKH) t f(SSCK) t r(SSCK)
SSCK (output) (CPOS = 1)
t w(SSCKL) t w(SSCKH)
SSCK (output) (CPOS = 0)
t w(SSCKL) t c(SSCK)
SSO (output)
t d(SSCK-SSIO)
SSI (input)
t su(SSIO-SSCK) t h(SSCK-SSIO)
4-Wire Bus Communication Mode, Master, CPHS = 0
VIH or VOH
SCS (output)
VIL or VOL t w(SSCKH) t f(SSCK) t r(SSCK)
SSCK (output) (CPOS = 1)
t w(SSCKL) t w(SSCKH)
SSCK (output) (CPOS =0)
t w(SSCKL) t c(SSCK)
SSO (output)
t d(SSCK-SSIO)
SSI (input)
t su(SSIO-SSCK) t h(SSCK-SSIO)
CPHS, CPOS: Bits in the SSMR register
Figure 5.15
I/O Timing of Serial Bus Interface (Master)
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5. Electrical Characteristics
J-Version, VCC = 5 V
4-Wire Bus Communication Mode, Slave, CPHS = 1
VIH or VOH
SCS (input)
VIL or VOL t su(SCS-SSCK) t w(SSCKH) t f(SSCK) t r(SSCK) t h(SSCK-SCS)
SSCK (input) (CPOS = 1)
t w(SSCKL) t w(SSCKH)
SSCK (input) (CPOS = 0)
t w(SSCKL) t c(SSCK)
SSO (input)
t su(SSIO-SSCK) t h(SSCK-SSIO)
SSI (output)
t en(SCS-SSI) t d(SSCK-SSIO) t dis(SCS-SSI)
4-Wire Bus Communication Mode, Slave, CPHS = 0 SCS (input)
VIH or VOH VIL or VOL t su(SCS-SSCK) t w(SSCKH) t f(SSCK) t r(SSCK) t h(SSCK-SCS)
SSCK (input) (CPOS = 1)
t w(SSCKL) t w(SSCKH)
SSCK (input) (CPOS = 0)
t w(SSCKL) t c(SSCK)
SSO (input)
t su(SSIO-SSCK)
t h(SSCK-SSIO)
SSI (output)
t en(SCS-SSI) t d(SSCK-SSIO) t dis(SCS-SSI)
CPHS, CPOS: Bits in the SSMR register
Figure 5.16
I/O Timing of Serial Bus Interface (Slave)
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5. Electrical Characteristics
J-Version, VCC = 5 V
t w(SSCKH) VIH or VOH
SSCK
VIL or VOL t w(SSCKL) t c(SSCK)
SSO (output)
t d(SSCK-SSIO)
SSI (input)
t su(SSIO-SSCK) t h(SSCK-SSIO)
Figure 5.17
I/O Timing of Serial Bus Interface (Synchronous Communication Mode)
MCU
Pin to be measured
30 pF
Figure 5.18
Switching Characteristic Measurement Circuit
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5. Electrical Characteristics
5.3 5.3.1
Electrical Characteristics (J-Version, VCC = 3 V) Electrical Characteristics
J-Version, VCC = 3 V
Table 5.32 Electrical Characteristics (1)
Standard Min. Typ. Max.
VCC = 3.0 to 3.6 V, VSS = 0 V at Topr = -40C to 85C, f(BCLK)= 32 MHz unless otherwise specified.
Symbol Parameter P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6 to P8_7, P9_0 to P9_7, P10_0 to P10_7 XOUT HIGH POWER LOW POWER HIGH POWER LOW POWER Measuring Condition Unit
VOH
HIGH Output Voltage
IOH = -1 mA
VCC-0.5
VCC
V
HIGH Output Voltage VOH HIGH Output Voltage
IOH = -0.1 mA IOH = -50 A With no load applied With no load applied
VCC-0.5 VCC-0.5 2.5 1.6
VCC VCC
V
XCOUT
V
VOL
LOW Output Voltage
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7 XOUT HIGH POWER LOW POWER HIGH POWER LOW POWER
IOL = 1mA
0.5
V
LOW Output Voltage VOL LOW Output Voltage
IOL = 0.1mA IOL = 50A With no load applied With no load applied 0 0
0.5 0.5
V
XCOUT
V
VT+-VT-
Hysteresis
TA0IN to TA4IN, TB0IN to TB5IN, INT0 to INT7, NMI, ADTRG, CTS0 to CTS3, SCL2, SDA2, CLK0 to CLK4, TA0OUT to TA4OUT, KI0 to KI3, RXD0 to RXD4, ZP, IDU, IDW, IDV, SD, INPC1_0 to INPC1_7, SSI0, SSCK0, SCS0, LIN0IN, CRX0, CRX1
RESET
0.4VCC
V
VT+-VTVT+-VT-
Hysteresis Hysteresis
1.8 0.8
V V
XIN P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7 XIN, RESET, CNVSS P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7 XIN, RESET, CNVSS P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6 to P8_7, P9_0 to P9_7, P10_0 to P10_7
IIH
HIGH Input Current
VI = 3V
4.0
A
IIL
LOW Input Current
VI = 0V
-4.0
A
RPULLUP
Pull-Up Resistance
VI = 0V
50
100
500
k
RfXIN RfXCIN VRAM
Feedback Resistance XIN Feedback Resistance XCIN RAM Retention Voltage At stop mode 2.0
3.0 25
M M V
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J-Version, VCC = 3 V
Table 5.33 Electrical Characteristics (2) Topr = -40C to 85C unless otherwise specified.
Symbol Parameter Measuring Condition
f(BCLK) = 32 MHz, XIN = 8 MHz (square wave), PLL multiply-by-8 125 kHz on-chip oscillator operates High speed mode f(BCLK) = 20 MHz, XIN = 20 MHz (square wave), 125 kHz on-chip oscillator operates f(BCLK) = 16 MHz, XIN = 16 MHz (square wave), 125 kHz on-chip oscillator operates Main clock stops 40 MHz on-chip oscillator operates 125 kHz on-chip oscillator operates 40 MHz on-chip oscillator No division mode Main clock stops 40 MHz on-chip oscillator operates 125 kHz on-chip oscillator operates Divide-by-8 Power Supply Current 125 kHz on-chip oscillator (VCC = 3.0 V to 3.6 mode V) In single-chip mode, the output pins are open and other pins are Low power mode VSS Main clock stops 40 MHz on-chip oscillator stops 125 kHz on-chip oscillator operates Divide-by-8 FMR22 = FMR23 = 1 (Low-current consumption read mode) f(BCLK) = 32 kHz On Flash memory (1) FMR22 = FMR23 = 1 (Low-current consumption read mode) Main clock stops 40 MHz on-chip oscillator stops 125 kHz on-chip oscillator operates Peripheral clock operates Topr = 25C Main clock stops 40 MHz on-chip oscillator stops 125 kHz on-chip oscillator operates Peripheral clock operates Topr = 85C Topr = 25C
Stop mode
Standard Min. Typ.
23
Max.
43
Unit
mA
20
38
mA
16
mA
20
38
mA
6
mA
190
580
A
ICC
200
A
25
A
Wait mode
55
A
2 30 20.0 30.0 3 6
12
A A
Topr = 85C f(BCLK) = 10 MHz, PM17 = 1 (one wait) VCC = 3.0 V f(BCLK) = 10 MHz, PM17 = 1 (one wait) VCC = 3.0 V
During flash memory program During flash memory erase Idet2 Idet0 Low Voltage Detection Dissipation Current Reset Area Detection Dissipation Current
mA mA
A A
Note: 1. This indicates the memory in which the program to be executed exists.
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5. Electrical Characteristics
J-Version, VCC = 3 V
5.3.2 Timing Requirements (Peripheral Functions and Others)
(VCC = 3 V, VSS = 0 V, at Topr = -40C to 85C unless otherwise specified)
5.3.2.1
Table 5.34
Symbol tw(RSTL)
Reset Input (RESET Input)
Reset Input (RESET Input)
Parameter
RESET input low pulse width
Standard Min. 10 Max.
Unit
s
RESET input t w(RTSL)
Figure 5.19
Reset Input (RESET Input)
5.3.2.2
Table 5.35
Symbol tc tw(H) tw(L) tr tf
External Clock Input
External Clock Input (XIN input) (1)
Parameter External clock input cycle time External clock input high pulse width External clock input low pulse width External clock rise time External clock fall time Standard Min. Max. 50 20 20 9 9 Unit ns ns ns ns ns
Note: 1. The condition is VCC = 3.0V.
XIN input tr t w(H) tf tc t w(L)
Figure 5.20
External Clock Input (XIN Input)
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5. Electrical Characteristics
J-Version, VCC = 3 V
Timing Requirements (VCC = 3 V, VSS = 0 V, at Topr = -40C to 85C unless otherwise specified)
5.3.2.3
Table 5.36
Symbol tc(TA) tw(TAH) tw(TAL)
Timer A Input
Timer A Input (Counter Input in Event Counter Mode)
Parameter TAiIN input cycle time TAiIN input high pulse width TAiIN input low pulse width Standard Min. Max. 150 60 60 Unit ns ns ns
Table 5.37
Symbol tc(TA) tw(TAH) tw(TAL)
Timer A Input (Gating Input in Timer Mode)
Parameter TAiIN input cycle time TAiIN input high pulse width TAiIN input low pulse width Standard Min. Max. 600 300 300 Unit ns ns ns
Table 5.38
Symbol tc(TA) tw(TAH) tw(TAL)
Timer A Input (External Trigger Input in One-shot Timer Mode)
Parameter TAiIN input cycle time TAiIN input high pulse width TAiIN input low pulse width Standard Min. Max. 300 150 150 Unit ns ns ns
Table 5.39
Symbol tw(TAH) tw(TAL)
Timer A Input (External Trigger Input in PWM Mode, Programmable Output Mode)
Parameter TAiIN input high pulse width TAiIN input low pulse width Standard Min. Max. 150 150 Unit ns ns
tc(TA) t w(TAH) TAiIN input t w(TAL) tc(UP) t w(UPH) TAiOUT input t w(UPL)
Figure 5.21
Timer A Input
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5. Electrical Characteristics
J-Version, VCC = 3 V
Timing Requirements (VCC = 3 V, VSS = 0 V, at Topr = -40C to 85C unless otherwise specified) Table 5.40
Symbol tc(TA) tsu(TAIN-TAOUT) tsu(TAOUT-TAIN) TAiIN input cycle time TAiOUT input setup time TAiIN input setup time
Timer A Input (Two-phase Pulse Input in Event Counter Mode)
Parameter Standard Min. Max. 2 500 500 Unit
s
ns ns
Two-phase pulse input in event counter mode tc(TA) TAiIN input tsu(TAIN-TAOUT) TAiOUT input tsu(TAOUT-TAIN) tsu(TAIN-TAOUT) tsu(TAOUT-TAIN)
Figure 5.22
Timer A Input (Two-Phase Pulse Input in Event Counter Mode)
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5. Electrical Characteristics
J-Version, VCC = 3 V
Timing Requirements (VCC = 3 V, VSS = 0 V, at Topr = -40C to 85C unless otherwise specified)
5.3.2.4
Table 5.41
Symbol tc(TB) tw(TBH) tw(TBL) tc(TB) tw(TBH) tw(TBL)
Timer B Input
Timer B Input (Counter Input in Event Counter Mode)
Parameter TBiIN input cycle time (counted on one edge) TBiIN input high pulse width (counted on one edge) TBiIN input low pulse width (counted on one edge) TBiIN input cycle time (counted on both edges) TBiIN input high pulse width (counted on both edges) TBiIN Input low pulse width (counted on both edges) Standard Min. 150 60 60 300 120 120 Max. Unit ns ns ns ns ns ns
Table 5.42
Symbol tc(TB) tw(TBH) tw(TBL)
Timer B Input (Pulse Period Measurement Mode)
Parameter TBiIN input cycle time TBiIN input high pulse width TBiIN input low pulse width Standard Min. 600 300 300 Max. Unit ns ns ns
Table 5.43
Symbol tc(TB) tw(TBH) tw(TBL)
Timer B Input (Pulse Width Measurement Mode)
Parameter TBiIN input cycle time TBiIN input high pulse width TBiIN input low pulse width Standard Min. 600 300 300 Max. Unit ns ns ns
tc(TB) t w(TBH) TBiIN input t w(TBL)
Figure 5.23
Timer B Input
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5. Electrical Characteristics
J-Version, VCC = 3 V
Timing Requirements (VCC = 3 V, VSS = 0 V, at Topr = -40C to 85C unless otherwise specified)
5.3.2.5
Table 5.44
Symbol tw(TSH) tw(TSL) tsu(TSUDA-TSUDB) tsu(TSUDB-TSUDA)
Timer S Input
Timer S Input (Two-phase Pulse Input in Two-phase Pulse Signal Processing Mode)
Parameter TSUDA, TSUDB input high pulse width TSUDA, TSUDB input low pulse width TSUDB input setup time TSUDA input setup time Standard Min. Max. 2 2 1 1 Unit s s s s
Two-phase pulse input in two-phase pulse signal processing mode
tw(TSH) tw(TSL)
TSUDA input
tsu(TSUDA-TSUDB) tw(TSH) tsu(TSUDA-TSUDB) tsu(TSUDB-TSUDA) tw(TSL)
TSUDB input
tsu(TSUDB-TSUDA)
Note: 1. When the TSUDA and TSUDB phases are interchanged, tsu(TSUDA-TSUDB) and tsu(TSUDB-TSUDA) are also interchanged.
Figure 5.24
Timer S Input (Two-phase Pulse Input in Two-phase Pulse Signal Processing Mode)
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5. Electrical Characteristics
J-Version, VCC = 3 V
Timing Requirements (VCC = 3 V, VSS = 0 V, at Topr = -40C to 85C unless otherwise specified)
5.3.2.6
Table 5.45
Symbol tc(CK) tw(CKH) tw(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D)
Serial Interface
Serial Interface
Parameter CLKi input cycle time CLKi input high pulse width CLKi input low pulse width TXDi output delay time TXDi hold time RXDi input setup time RXDi input hold time 0 100 90 Standard Min. 300 150 150 160 Max. Unit ns ns ns ns ns ns ns
tc(CK) t w(CKH) CLKi t w(CKL) th(C-Q) TXDi td(C-Q) RXDi tsu(D-C) th(C-D)
Figure 5.25
Serial Interface
5.3.2.7
Table 5.46
Symbol tw(INH) tw(INL)
External Interrupt INTi Input
External Interrupt INTi Input
Parameter
INTi Input HIGH Pulse Width INTi Input LOW Pulse Width
Standard Min. 380 380 Max.
Unit ns ns
t w(INL) INTi input t w(INH)
Figure 5.26
External Interrupt INTi Input
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5. Electrical Characteristics
J-Version, VCC = 3 V
Timing Requirements (VCC = 3 V, VSS = 0 V, at Topr = -40C to 85C unless otherwise specified)
5.3.2.8
Table 5.47
Symbol tBUF tHD;STA tLOW tR tHD;DAT tHIGH fF tsu;DAT tsu;STA tsu;STO
Multi-master I2C-bus
Multi-master I2C-bus
Parameter Bus free time Hold time in start condition Hold time in SCL clock 0 status SCL, SDA signals' rising time Data hold time Hold time in SCL clock 1 status SCL, SDA signals' falling time Data setup time Setup time in restart condition Stop condition setup time 250 4.7 4.0 0 4.0 300 Standard Clock Mode Min. 4.7 4.0 4.7 1000 Max. High-speed Clock Mode Min. 1.3 0.6 1.3 20 + 0.1 Cb 0 0.6 20 + 0.1 Cb 100 0.6 0.6 300 300 0.9 Max. Unit
s s s
ns
s s
ns ns
s s
SDA
t BUF t HD;STA t LOW
s
t su;STO
tR
tF
SCL
p
Sr
p
t HD;STA
t HD;DTA
t HIGH
t su;DTA
t su;STA
Figure 5.27
Multi-master I2C-bus
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5. Electrical Characteristics
J-Version, VCC = 3 V
Timing Requirements (VCC = 3 V, VSS = 0 V, at Topr = -40C to 85C unless otherwise specified)
5.3.2.9
Table 5.48
Symbol tc(SSCK) tw(SSCKH) tw(SSCKL) tr(SSCK)
Serial bus interface
Serial Bus Interface
Characteristic SSCK clock cycle time SSCK clock high pulse width SSCK clock low pulse width Master SSCK clock rising time Slave Master SSCK clock falling time Slave 100 1 Slave Slave 1 tCYC + 50 (1) 1 tCYC + 50 (1) 1 3.0 V VCC 5.5 V 3.0 V VCC 5.5 V 1.5 tCYC + 100 (1) 1.5 tCYC + 100 (1) 1 1 1 Measurement condition Value Min. 250 0.4 0.4 0.6 0.6 1 Typ. Max. Unit ns tc(SSCK) tc(SSCK) tCYC (1)
s
tf(SSCK)
tCYC (1)
s
tsu(SSIO-SSCK) SSO, SSI data input setup time th(SSCK-SSIO) SSO, SSI data input hold time
ns tCYC (1) ns ns tCYC (1) ns ns
tsu(SCS-SSCK) SCS setup time th(SSCK-SCS) td(SSCK-SSIO) ten(SCS-SSI) tdis(SCS-SSI) Note: 1.
SCS hold time
SS0, SSI data output delay time SSI output enable time SSI output disable time
1 tCYC is 1/f1 (s).
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5. Electrical Characteristics
J-Version, VCC = 3 V
4-Wire Bus Communication Mode, Master, CPHS = 1
VIH or VOH
SCS (output)
VIL or VOL t w(SSCKH) t f(SSCK) t r(SSCK)
SSCK (output) (CPOS = 1)
t w(SSCKL) t w(SSCKH)
SSCK (output) (CPOS = 0)
t w(SSCKL) t c(SSCK)
SSO (output)
t d(SSCK-SSIO)
SSI (input)
t su(SSIO-SSCK) t h(SSCK-SSIO)
4-Wire Bus Communication Mode, Master, CPHS = 0
VIH or VOH
SCS (output)
VIL or VOL t w(SSCKH) t f(SSCK) t r(SSCK)
SSCK (output) (CPOS = 1)
t w(SSCKL) t w(SSCKH)
SSCK (output) (CPOS =0)
t w(SSCKL) t c(SSCK)
SSO (output)
t d(SSCK-SSIO)
SSI (input)
t su(SSIO-SSCK) t h(SSCK-SSIO)
CPHS, CPOS: Bits in the SSMR register
Figure 5.28
I/O Timing of Serial Bus Interface (Master)
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5. Electrical Characteristics
J-Version, VCC = 3 V
4-Wire Bus Communication Mode, Slave, CPHS = 1
VIH or VOH
SCS (input)
VIL or VOL t su(SCS-SSCK) t w(SSCKH) t f(SSCK) t r(SSCK) t h(SSCK-SCS)
SSCK (input) (CPOS = 1)
t w(SSCKL) t w(SSCKH)
SSCK (input) (CPOS = 0)
t w(SSCKL) t c(SSCK)
SSO (input)
t su(SSIO-SSCK) t h(SSCK-SSIO)
SSI (output)
t en(SCS-SSI) t d(SSCK-SSIO) t dis(SCS-SSI)
4-Wire Bus Communication Mode, Slave, CPHS = 0 SCS (input)
VIH or VOH VIL or VOL t su(SCS-SSCK) t w(SSCKH) t f(SSCK) t r(SSCK) t h(SSCK-SCS)
SSCK (input) (CPOS = 1)
t w(SSCKL) t w(SSCKH)
SSCK (input) (CPOS = 0)
t w(SSCKL) t c(SSCK)
SSO (input)
t su(SSIO-SSCK)
t h(SSCK-SSIO)
SSI (output)
t en(SCS-SSI) t d(SSCK-SSIO) t dis(SCS-SSI)
CPHS, CPOS: Bits in the SSMR register
Figure 5.29
I/O Timing of Serial Bus Interface (Slave)
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5. Electrical Characteristics
J-Version, VCC = 3 V
t w(SSCKH) VIH or VOH
SSCK
VIL or VOL t w(SSCKL) t c(SSCK)
SSO (output)
t d(SSCK-SSIO)
SSI (input)
t su(SSIO-SSCK) t h(SSCK-SSIO)
Figure 5.30
I/O Timing of Serial Bus Interface (Synchronous Communication Mode)
MCU
Pin to be measured
30 pF
Figure 5.31
Switching Characteristic Measurement Circuit
REJ03B0267-0101 Jul 23, 2010
Rev.1.01
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5. Electrical Characteristics
K-Version
5.4 5.4.1
Table 5.49
Electrical Characteristics (K-Version, Common to 3 V and 5 V) Absolute Maximum Rating
Absolute Maximum Ratings
Symbol VCC AVCC VREF VI
Characteristic Supply voltage Analog supply voltage Analog reference voltage Input voltage P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7 XIN, RESET, CNVSS, VREF Output voltage P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7 XOUT
Condition VCC = AVCC VCC = AVCC
Value -0.3 to 6.5 -0.3 to 6.5
-0.3 to VCC + 0.1 (1)
Unit V V V
-0.3 to VCC + 0.3
V
VO
-0.3 to VCC + 0.3
V
Pd Topr
Power consumption
-40C Topr 85C 85C < Topr 125C
300 250 -40 to 125
mW mW
Operating While CPU operation temperature range While flash memory program and erase operation Storage temperature range Maximum value is 6.5 V.
Programming area Data area
0 to 60 -40 to 125 -65 to 150
C
Tstg
Note:
C
1.
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5. Electrical Characteristics
K-Version
5.4.2
Table 5.50
Symbol VCC AVCC VSS AVSS Supply voltage Analog supply voltage Ground voltage Analog ground voltage P0_0 to P0_7, P1_0 to P1_7, Input level 0.50 VCC P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, Input level 0.70 VCC High level input P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7 voltage XIN, RESET, CNVSS SDAMM, SCLMM When I2C-bus input level selected 0.7 VCC
Recommended Operating Conditions
Operating Conditions (1)
Characteristic Value Min. 3.0 VCC 0 0 VCC Typ. Max. 5.5 Unit V V V V V
VCC = 3.0 V to 5.5 V, Topr = -40 C to 125 C unless otherwise specified.
0.85VCC 0.8 VCC 0.7 VCC 2.1 0
VCC VCC VCC VCC 0.3 VCC
V
VIH
V V V
When SMBUS input level selected
VIL
P0_0 to P0_7, P1_0 to P1_7, Input level 0.50 VCC P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, Input level 0.70 VCC Low level input P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7 voltage XIN, RESET, CNVSS SDAMM, SCLMM When I2C-bus input level selected When SMBUS input level selected
0
0.45VCC
V
0 0 0
0.2 VCC 0.3 VCC 0.8 -80.0
V V V
IOH(sum) High peak
output current
Sum of IOH(peak) at P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6 to P8_7, P9_0 to P9_7, P10_0 to P10_7
mA
IOH(peak)
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to High level peak P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, output current P8_6 to P8_7, P9_0 to P9_7, P10_0 to P10_7 High level P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to average output P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6 to P8_7, P9_0 to P9_7, P10_0 to P10_7 current (2) Low peak output current Sum of IOL(peak) at P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7
-10.0
mA
IOH(avg)
-5.0
mA
IOL(sum)
80.0
mA
IOL(peak)
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to Low level peak P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, output current P9_0 to P9_7, P10_0 to P10_7 Low level P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to average output P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7 current (2) Main clock input oscillation frequency (2) Sub clock oscillation oscillator frequency PLL clock oscillation frequency CPU operation frequency Wait time to stabilize PLL frequency synthesizer
(2)
10.0
mA
IOL(avg) f(XIN) f(XCIN) f(PLL) f(BCLK) tsu(PLL)
5.0 0 32.768 10 0 20 50 32 32 1
mA MHz kHz MHz MHz ms
Notes: 1. The mean output current is the mean value within 100ms. 2. Refer to "Figure 5.1 "Main clock input oscillation frequency, PLL clock oscillation frequency"" for the relationship between main clock oscillation frequency/PLL clock oscillation frequency and supply voltage.
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Main clock input oscillation frequency
f(XIN) maximum operating frequency [MHz] f(XIN) maximum operating frequency [MHz]
PLL clock oscillation frequency
32.0
20.0 MHz 20.0
32.0 MHz
10.0
10.0
0.0 3.0 5.5
0.0 3.0 5.5
Vcc [V] (main clock: no division)
Vcc [V] (PLL clock oscillation)
Figure 5.32
Main Clock Input Oscillation Frequency, PLL Clock Oscillation Frequency
Table 5.51
Recommended Operating Conditions (2/2) (1)
VCC = 3.0 to 5.5 V, VSS = 0 V, and Topr = -40C to 125C unless otherwise specified. The ripple voltage must not exceed Vr(VCC) and/or dVr(VCC)/dt. Symbol Vr(VCC) dVr(VCC)/dt Allowable ripple voltage Parameter VCC = 5.0 V VCC = 3.0 V VCC = 5.0 V VCC = 3.0 V Standard Min. Typ. Max. 0.5 0.3 0.3 0.3 Unit Vp-p Vp-p V/ms V/ms
Ripple voltage falling gradient
Note: 1. The device is operationally guaranteed under these operating conditions.
VCC
V r( VCC )
Figure 5.33
Ripple Waveform
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5.4.3 A/D Conversion Characteristics
Table 5.52 A/D Conversion Characteristics (1) VCC = AVCC = VREF = 3.0 to 5.5 V, VSS = AVSS = 0 V at Topr = -40C to 125C unless otherwise specified.
Symbol --- INL Resolution Integral Non-Linearity Error Parameter Measuring Condition VREF = VCC VREF = VCC = 5.0 V (2) VREF = VCC = 3.3 V (2) VREF = VCC = 5.0 V (2) VREF = VCC = 3.3 V (2) 4.0 V VCC 5.5 V AD A/D operating clock frequency 3.2 V VCC 4.0 V 3.0 V VCC 3.2 V --- DNL --- --- tCONV tsamp VREF VIA Tolerance Level Impedance Differential Non-Linearity Error Offset Error (4) Gain Error (4) 10-bit Conversion Time Sampling time Reference Voltage Analog Input Voltage (3)
(2) (2) (2)
Standard Min. Typ. Max. 10 3 5 3 5 2 2 2 3 1 3 3 1.60 0.6 3.0 0 VCC VREF 25 16 10
Unit Bits LSB LSB LSB LSB MHz MHz MHz k LSB LSB LSB s s V V
---
Absolute Accuracy
VREF = VCC = 5V, AD = 25 MHz
Notes: 1. Use when AVCC = VCC 2. Flash memory rewrite disabled. Except for the analog input pin, set the pins to be measured as input ports and connect them to VSS. See Figure 5.34 "A/D Accuracy Measure Circuit". 3. When analog input voltage is over reference voltage, the result of A/D conversion is 3FFh.
AN
Analog input
P0 to P10
AN: One of the analog input pin P0 to P10: I/O pins other than AN
Figure 5.34
A/D Accuracy Measure Circuit
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5.4.4 D/A Conversion Characteristics
Table 5.53 D/A Conversion Characteristics VCC = AVCC = VREF = 3.0 to 5.5 V, VSS = AVSS = 0 V at Topr = -40C to 125C unless otherwise specified.
Symbol tSU RO IVREF Resolution Absolute Accuracy Setup Time Output Resistance Reference Power Supply Input Current See Notes and
1 2
Parameter
Measuring Condition
Standard Min. Typ. Max. 8 2.5 3 5 6 8.2 1.5
Unit Bits LSB s k mA
Notes: 1. This applies when using one D/A converter, with the D/A register for the unused D/A converter set to 00h. 2. The current consumption of the A/D converter is not included. Also, the IVREF of the D/A converter will flow even if the ADSTBY bit in the ADCON1 register is 0 (A/D operation stopped (standby)).
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5.4.5 Flash Memory Electrical Characteristics
Table 5.54 CPU Clock When Operating Flash Memory (f(BCLK)) VCC = 3.0 to 5.5 V at Topr = -40C to 125C, unless otherwise specified.
Symbol f(SLOW_R) Parameter CPU rewrite mode Slow read mode Low current consumption read mode Data flash read fC Conditions Standard Min. Typ. Max. 16 (1) 5 35 20
(3)
Unit MHz MHz kHz MHz
(2)
Notes: 1. Set the PM17 bit in the PM1 register to 1 (one wait). 2. When the frequency is over this value, set the FMR17 bit in the FMR1 register to 0 (one wait) or the PM17 bit in the PM1 register to 1 (one wait) 3. Set the PM17 bit in the PM1 register to 1 (one wait). No wait states are required if the 125 kHz on-chip oscillator clock or sub clock is used as the clock source of the CPU clock.
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Table 5.55 Flash Memory (Program ROM 1, 2) Electrical Characteristics VCC = 3.0 to 5.5 V at Topr = 0C to 60C, unless otherwise specified.
Symbol td(SR-SUS) tPS Parameter Program/erase cycles (1, 3, 4) Two words program time Lock bit program time Block erase time Time delay from suspend request until suspend Interval from erase start/restart until following suspend request Suspend interval necessary for auto-erasure to complete (7) Time from suspend until erase restart Program, erase voltage Read voltage Program, erase temperature Flash Memory Circuit Stabilization Wait Time Data hold time (6) Ambient temperature = 55C 20 Topr = -40C to 125C 3.0 3.0 0 0 20 130 + --------------f ( BCLK ) 5.5 5.5 60 50 Conditions VCC = 3.3 V, Topr = 25C VCC = 3.3 V, Topr = 25C VCC = 3.3 V, Topr = 25C VCC = 3.3 V, Topr = 25C Standard Min. 1,000 (2) 150 70 0.2 4000 3000 3.0 35 + --------------f ( BCLK ) Typ. Max. Unit times s s s ms s ms s V V C s year
Notes: 1. Definition of program and erase cycles: The program and erase cycles refer to the number of per-block erasures. If the program and erase cycles are n (n = 1,000), each block can be erased n times. For example, if a 64 Kbyte block is erased after writing two word data 16,384 times, each to a different address, this counts as one program and erase cycles. Data cannot be written to the same address more than once without erasing the block (rewrite prohibited). 2. Cycles to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed). 3. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential addresses in turn so that as much of the block as possible is used up before performing an erase operation. It is advisable to retain data on the erasure cycles of each block and limit the number of erase operations to a certain number. 4. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase command at least three times until the erase error does not occur. 5. Customers desiring program/erase failure rate information should contact a Renesas Electronics sales office. 6. The data hold time includes time that the power supply is off or the clock is not supplied. 7. After an erase start or erase restart, if an interval of at least 20 ms is not set before the next suspend request, the erase sequence cannot be completed.
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Table 5.56 Flash Memory (Data Flash) Electrical Characteristics VCC = 3.0 to 5.5 V at Topr = -40C to 125C, unless otherwise specified.
Symbol Parameter Program/erase cycles (1, 3, 4) Two words program time Lock bit program time Block erase time Conditions VCC = 3.3 V, Topr = 25C VCC = 3.3 V, Topr = 25C VCC = 3.3 V, Topr = 25C VCC = 3.3 V, Topr = 25C Standard Min. 10,000 (2) 300 140 0.2 4000 3000 3.0 35 + --------------f ( BCLK ) 0 20 130 + --------------f ( BCLK ) 3.0 3.0 -40 Ambient temperature = 55 C 20 5.5 5.5 125 50 Typ. Max. Unit times s s s ms s ms s V V C s year
td(SR-SUS) Time delay from suspend request until suspend tPS Interval from erase start/restart until following suspend request Suspend interval necessary for auto-erasure to complete (7) Time from suspend until erase restart Program, erase voltage Read voltage Program, erase temperature Flash Memory Circuit Stabilization Wait Time Data hold time (6)
Notes: 1. Definition of program and erase cycles The program and erase cycles refer to the number of per-block erasures. If the program and erase cycles are n (n = 10,000), each block can be erased n times. For example, if a 4 Kbyte block is erased after writing two word data 1,024 times, each to a different address, this counts as one program and erase cycles. Data cannot be written to the same address more than once without erasing the block (rewrite prohibited). 2. Cycles to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed). 3. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example, when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 256 groups before erasing them all in one operation. In addition, averaging the erasure cycles between blocks A and B can further reduce the actual erasure cycles. It is also advisable to retain data on the erasure cycles of each block and limit the number of erase operations to a certain number. 4. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase command at least three times until the erase error does not occur. 5. Customers desiring program/erase failure rate information should contact a Renesas Electronics sales office. 6. The data hold time includes time that the power supply is off or the clock is not supplied. 7. After an erase start or erase restart, if an interval of at least 20 ms is not set before the next suspend request, the erase sequence cannot be completed.
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5.4.6 E2PROM Emulation Data Flash
Table 5.57 E2PROM Emulation Data Flash Electrical Characteristics VCC = 3.0 to 5.5 V at Topr = -40C to 125C, unless otherwise specified.
Symbol
-- -- -- -- tPS --
Characteristic
Program/erase cycles (1) Word program time (2-byte program) Read time (2-byte read) Block erase time (32-byte block) Flash memory circuit stabilization wait time (sleep mode to normal mode) Data hold time (2) Ambient temperature = 55C (3, 4)
Value Min.
100000 100 15 35 20 2000 1 200 50
Typ.
Max.
Unit
times s s ms s years
Notes: 1. Definition of program/erase cycles definition This value represents the number of erasure per block. If the flash memory is programmed/erased n times, each block can be erased n times. i.e. If a word write is performed in different 16 addresses in a block and then the block is erased, it is considered the programming/erasure is performed just once. However a write in the same address more than once for one erasure is disabled. (overwrite disabled). 2. The data hold time includes the periods when the supply voltage is not applied and no clock is provided. 3. This data hold time includes (3000) hours in Ambient temperature = 125C. 4. Please contact a Renesas Electronics sales office regarding data retention time other than the above.
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5.4.7 Voltage Detector and Power Supply Circuit Electrical Characteristics
Table 5.58 Voltage Detector 0 Electrical Characteristics The measurement condition is VCC = 3.0 to 5.5 V, Topr = -40C to 125C, unless otherwise specified.
Symbol Vdet0 td(E-A) Parameter Voltage detection level Vdet0 Waiting time until voltage detector operation starts (1) Condition When VCC is falling. VCC = 3.0 to 5.0 V Standard Min. 2.70 Typ. 2.85 Max. 3.00 100 Unit V s
Note:
1. Necessary time until the voltage detector operates when setting to 1 again after setting the VC25 bit in the VCR2 register to 0.
Table 5.59 Voltage Detector 2 Electrical Characteristics The measurement condition is VCC = 3.0 to 5.5 V, Topr = -40C to 125C, unless otherwise specified.
Symbol Vdet2_0 Vdet2_1 Vdet2_2 Vdet2_3 Vdet2_4 Vdet2_5 Vdet2_6 Vdet2_7 td(E-A) Parameter Voltage detection level Vdet2_0 Voltage detection level Vdet2_1 Voltage detection level Vdet2_2 Voltage detection level Vdet2_3 Voltage detection level Vdet2_4 Voltage detection level Vdet2_5 Voltage detection level Vdet2_6 Voltage detection level Vdet2_7 Hysteresis width at the rising of VCC in voltage detector 2 Waiting time until voltage detector operation starts (1) VCC = 3.0 to 5.0 V When VCC is falling 3.51 Condition Standard Min. Typ. 3.21 3.36 3.51 3.66 3.81 3.96 4.10 4.25 0.15 100 4.11 Max. Unit V V V V V V V V V s
Note:
1. Necessary time until the voltage detector operates after setting to 1 again after setting the VC27 bit in the VCR2 register to 0.
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Table 5.60 Power-On Reset Circuit The measurement condition is Topr = -40C to 125C, unless otherwise specified.
Symbol trth tfth Vpor tw(por) Note: Parameter External power VCC rise gradient External power VCC fall gradient Voltage at which power-on reset enabled
(1)
Condition
Standard Min. 2.0 Typ. Max.
Unit
50000 mV/ms 50000 mV/ms 0.1 V ms
Hold time at which power-on reset enabled
1.0
1.
To use the power-on reset function, enable voltage monitor 0 reset by setting the LVDAS bit in the OFS1 address to 0.
Vdet0 External Power VCC Vpor tw(por) t rth t fth t rth
Vdet0
Internal reset signal 1 fOCO-S 1 fOCO-S
x 128
x 128
Figure 5.35
Power-On Reset Circuit Electrical Characteristics
Table 5.61
Symbol td(P-R) td(R-S) td(W-S)
Power Supply Circuit Timing Characteristics
Parameter Measuring Condition Standard Min. Typ. Max. 5 300 300 Unit ms s s
Time for Internal Power Supply Stabilization VCC = 3.0 V to 5.5V During Powering-On STOP Release Time Low Power Mode Wait Mode Release Time
Note: 1. When VCC = 5 V.
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Recommended operating voltage
Time to stabilize internal supply voltage during powering-on
t d(P-R)
VCC
td(P-R) CPU clock
t d(R-S)
(a) Interrupt to exit from stop mode (b) Interrupt to exit from wait mode
STOP release time
Low power consumption mode wait mode exit time
t d(W-S)
CPU clock (a) (b) td(R-S) td(W-S)
t d(E-A)
Voltage detection circuit operation start time
VC25, VC27
Stop td(E-A) Operate
Voltage detection circuit
Figure 5.36
Power Supply Circuit Timing Diagram
5.4.8
Oscillation Circuit Electrical Characteristics
Table 5.62 On-chip Oscillator Oscillation Circuit Electrical Characteristics VCC = 3.0 to 5.5 V, Topr = -40C to 125C, unless otherwise specified
Symbol fOCO-S fOCO40M Characteristic 125 kHz on-chip oscillator oscillation frequency 40 kHz on-chip oscillator oscillation frequency Value Min. 100 32 Typ. 125 40 Max. 150 48 kHz MHz Unit
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5.5 5.5.1
Electrical Characteristics (K-Version, VCC = 5 V) Electrical Characteristics
K-Version, VCC = 5 V
Table 5.63 Electrical Characteristics (1)
Standard Min. Typ. Max.
VCC = 4.2 to 5.5 V, VSS = 0 V at Topr = -40C to 125C, f(BCLK) = 32 MHz unless otherwise specified.
Symbol Parameter P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6 to P8_7, P9_0 to P9_7, P10_0 to P10_7 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6 to P8_7, P9_0 to P9_7, P10_0 to P10_7 XOUT HIGH POWER LOW POWER HIGH Output Voltage XCOUT HIGH POWER LOW POWER P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7 HIGH POWER LOW Output Voltage VOL LOW Output Voltage XCOUT XOUT LOW POWER HIGH POWER LOW POWER Measuring Condition Unit
VOH
HIGH Output Voltage
IOH=-5 mA
VCC-2.0
VCC
V
VOH
HIGH Output Voltage
IOH = -200 A IOH = -1 mA IOH = -0.5 mA With no load applied With no load applied
VCC--0.3 VCC--2.0 VCC--2.0 2.5 1.6
VCC
V
HIGH Output Voltage VOH
VCC VCC
V
V
VOL
LOW Output Voltage
IOL = 5 mA
2.0
V
VOL
LOW Output Voltage
IOL = 200 A
0.45
V
IOL = 1 mA IOL = 0.5 mA With no load applied With no load applied 0 0
2.0 V 2.0 V
VT+-VT-
Hysteresis
TA0IN to TA4IN, TB0IN to TB5IN, INT0 to INT7, NMI, ADTRG, CTS0 to CTS3, SCL2, SDA2, CLK0 to CLK4, TA0OUT to TA4OUT, KI0 to KI3, RXD0 to RXD4, ZP, IDU, IDW, IDV, SD, INPC1_0 to INPC1_7, SSI0, SSCK0, SCS0, LIN0IN, CRX0, CRX1
RESET
0.2
0.4VCC
V
VT+-VTVT+-VT-
Hysteresis Hysteresis
0.2 0.2
2.5 0.8
V V
XIN P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7 XIN, RESET, CNVSS P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 toP9_7, P10_0 to P10_7 XIN, RESET, CNVSS P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6 to P8_7, P9_0 to P9_7, P10_0 to P10_7
IIH
HIGH Input Current
VI = 5 V
5.0
A
IIL
LOW Input Current
VI = 0 V
-5.0
A
RPULLUP
Pull-Up Resistance
VI = 0 V
30
50
170
k
RfXIN RfXCIN VRAM
Feedback Resistance XIN Feedback Resistance XCIN RAM Retention Voltage At stop mode 2.0
1.5 15
M M V
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K-Version, VCC = 5 V
Table 5.64
Topr = -40C to 125C unless otherwise specified.
Parameter Measuring Condition
f(BCLK) = 32 MHz, XIN = 8 MHz (square wave), PLL multiply-by-8 125 kHz on-chip oscillator operates f(BCLK) = 20 MHz, High speed mode XIN = 20 MHz (square wave), 125 kHz on-chip oscillator operates f(BCLK) = 16 MHz, XIN = 16 MHz (square wave), 125 kHz on-chip oscillator operates Main clock stops 40 MHz on-chip oscillator operates 125 kHz on-chip oscillator operates 40 MHz on-chip oscillator No division mode Main clock stops 40 MHz on-chip oscillator operates 125 kHz on-chip oscillator operates Divide-by-8 Main clock stops 40 MHz on-chip oscillator stops 125 kHz on-chip oscillator 125 kHz on-chip oscillator operates Divide-by-8 mode FMR22 = FMR23 = 1 (Low-current consumption
Electrical Characteristics (2)
Symbol
Standard Unit Min. Typ. Max.
25 45 mA
21
39
mA
17
mA
21
39
mA
6
mA
190
580
A
read mode)
Power Supply Current (VCC = 4.2 V to 5.5 V) In single-chip mode, the output pins are open and other pins are VSS Low power mode f(BCLK) = 32 kHz On Flash memory (2) FMR22 = FMR23 = 1 (Low-current consumption 200
A
ICC
read mode)
Main clock stops 40 MHz on-chip oscillator stops 125 kHz on-chip oscillator operates Peripheral clock operates Topr = 25C Main clock stops 40 MHz on-chip oscillator stops 125 kHz on-chip oscillator operates Peripheral clock operates Topr = 105C Main clock stops 40 MHz on-chip oscillator stops 125 kHz on-chip oscillator operates Peripheral clock operates Topr = 125C Topr = 25C Stop mode Topr = 105C Topr = 125C
25
A
Wait mode
85
A
125
A A A A
3 60 100 20.0 30.0 3 6
15
During flash memory program During flash memory erase
Idet2 Idet0 Low Voltage Detection Dissipation Current Reset Area Detection Dissipation Current
f(BCLK) = 10 MHz, PM17 = 1 (one wait) VCC = 5.0 V f(BCLK) = 10 MHz, PM17 = 1 (one wait) VCC = 5.0 V
mA mA
A A
Note: 1. This indicates the memory in which the program to be executed exists.
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5. Electrical Characteristics
K-Version, VCC = 5 V
5.5.2 Timing Requirements (Peripheral Functions and Others)
(VCC = 5 V, VSS = 0 V, at Topr = -40C to 125C unless otherwise specified)
5.5.2.1
Table 5.65
Symbol tw(RSTL)
Reset Input (RESET Input)
Reset Input (RESET Input)
Parameter
RESET input low pulse width
Standard Min. 10 Max.
Unit
s
RESET input t w(RTSL)
Figure 5.37
Reset Input (RESET Input)
5.5.2.2
Table 5.66
Symbol tc tw(H) tw(L) tr tf
External Clock Input
External Clock Input (XIN input) (1)
Parameter External clock input cycle time External clock input high pulse width External clock input low pulse width External clock rise time External clock fall time Standard Min. Max. 50 20 20 9 9 Unit ns ns ns ns ns
Note: 1. The condition is VCC = 5.0V.
XIN input tr t w(H) tf tc t w(L)
Figure 5.38
External Clock Input (XIN Input)
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5. Electrical Characteristics
K-Version, VCC = 5 V
Timing Requirements (VCC = 5 V, VSS = 0 V, at Topr = -40C to 125C unless otherwise specified)
5.5.2.3
Table 5.67
Symbol tc(TA) tw(TAH) tw(TAL)
Timer A Input
Timer A Input (Counter Input in Event Counter Mode)
Parameter TAiIN input cycle time TAiIN input high pulse width TAiIN input low pulse width Standard Min. Max. 100 40 40 Unit ns ns ns
Table 5.68
Symbol tc(TA) tw(TAH) tw(TAL)
Timer A Input (Gating Input in Timer Mode)
Parameter TAiIN input cycle time TAiIN input high pulse width TAiIN input low pulse width Standard Min. Max. 400 200 200 Unit ns ns ns
Table 5.69
Symbol tc(TA) tw(TAH) tw(TAL)
Timer A Input (External Trigger Input in One-shot Timer Mode)
Parameter TAiIN input cycle time TAiIN input high pulse width TAiIN input low pulse width Standard Min. Max. 200 100 100 Unit ns ns ns
Table 5.70
Symbol tw(TAH) tw(TAL)
Timer A Input (External Trigger Input in PWM Mode, Programmable Output Mode)
Parameter TAiIN input high pulse width TAiIN input low pulse width Standard Min. Max. 100 100 Unit ns ns
tc(TA) t w(TAH) TAiIN input t w(TAL) tc(UP) t w(UPH) TAiOUT input t w(UPL)
Figure 5.39
Timer A Input
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5. Electrical Characteristics
K-Version, VCC = 5 V
Timing Requirements (VCC = 5 V, VSS = 0 V, at Topr = -40C to 125C unless otherwise specified) Table 5.71
Symbol tc(TA) tsu(TAIN-TAOUT) tsu(TAOUT-TAIN) TAiIN input cycle time TAiOUT input setup time TAiIN input setup time
Timer A Input (Two-phase Pulse Input in Event Counter Mode)
Parameter Standard Min. Max. 800 200 200 Unit ns ns ns
Two-phase pulse input in event counter mode tc(TA) TAiIN input tsu(TAIN-TAOUT) TAiOUT input tsu(TAOUT-TAIN) tsu(TAIN-TAOUT) tsu(TAOUT-TAIN)
Figure 5.40
Timer A Input (Two-Phase Pulse Input in Event Counter Mode)
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5. Electrical Characteristics
K-Version, VCC = 5 V
Timing Requirements (VCC = 5 V, VSS = 0 V, at Topr = -40C to 125C unless otherwise specified)
5.5.2.4
Timer B Input
Table 5.72
Symbol tc(TB) tw(TBH) tw(TBL) tc(TB) tw(TBH) tw(TBL)
Timer B Input (Counter Input in Event Counter Mode)
Parameter TBiIN input cycle time (counted on one edge) TBiIN input high pulse width (counted on one edge) TBiIN input low pulse width (counted on one edge) TBiIN input cycle time (counted on both edges) TBiIN input high pulse width (counted on both edges) TBiIN Input low pulse width (counted on both edges) Standard Min. 100 40 40 200 80 80 Max. Unit ns ns ns ns ns ns
Table 5.73
Symbol tc(TB) tw(TBH) tw(TBL)
Timer B Input (Pulse Period Measurement Mode)
Parameter TBiIN input cycle time TBiIN input high pulse width TBiIN input low pulse width Standard Min. 400 200 200 Max. Unit ns ns ns
Table 5.74
Symbol tc(TB) tw(TBH) tw(TBL)
Timer B Input (Pulse Width Measurement Mode)
Parameter TBiIN input cycle time TBiIN input high pulse width TBiIN input low pulse width Standard Min. 400 200 200 Max. Unit ns ns ns
tc(TB) t w(TBH) TBiIN input t w(TBL)
Figure 5.41
Timer B Input
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5. Electrical Characteristics
K-Version, VCC = 5 V
Timing Requirements (VCC = 5 V, VSS = 0 V, at Topr = -40C to 125C unless otherwise specified)
5.5.2.5
Table 5.75
Symbol tw(TSH) tw(TSL) tsu(TSUDA-TSUDB) tsu(TSUDB-TSUDA)
Timer S Input
Timer S Input (Two-phase Pulse Input in Two-phase Pulse Signal Processing Mode)
Parameter TSUDA, TSUDB input high pulse width TSUDA, TSUDB input low pulse width TSUDB input setup time TSUDA input setup time Standard Min. Max. 2 2 1 1 Unit s s s s
Two-phase pulse input in two-phase pulse signal processing mode
tw(TSH) tw(TSL)
TSUDA input
tsu(TSUDA-TSUDB) tw(TSH) tsu(TSUDA-TSUDB) tsu(TSUDB-TSUDA) tw(TSL)
TSUDB input
tsu(TSUDB-TSUDA)
Note: 1. When the TSUDA and TSUDB phases are interchanged, tsu(TSUDA-TSUDB) and tsu(TSUDB-TSUDA) are also interchanged.
Figure 5.42
Timer S Input (Two-phase Pulse Input in Two-phase Pulse Signal Processing Mode)
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5. Electrical Characteristics
K-Version, VCC = 5 V
Timing Requirements (VCC = 5 V, VSS = 0 V, at Topr = -40C to 125C unless otherwise specified)
5.5.2.6
Table 5.76
Symbol tc(CK) tw(CKH) tw(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D)
Serial Interface
Serial Interface
Parameter CLKi input cycle time CLKi input high pulse width CLKi input low pulse width TXDi output delay time TXDi hold time RXDi input setup time RXDi input hold time 0 70 90 Standard Min. 200 100 100 80 Max. Unit ns ns ns ns ns ns ns
tc(CK) t w(CKH) CLKi t w(CKL) th(C-Q) TXDi td(C-Q) RXDi tsu(D-C) th(C-D)
Figure 5.43
Serial Interface
5.5.2.7
Table 5.77
Symbol tw(INH) tw(INL)
External Interrupt INTi Input
External Interrupt INTi Input
Parameter
INTi input high pulse width INTi input low pulse width
Standard Min. 250 250 Max.
Unit ns ns
t w(INL) INTi input t w(INH)
Figure 5.44
External Interrupt INTi Input
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5. Electrical Characteristics
K-Version, VCC = 5 V
Timing Requirements (VCC = 5 V, VSS = 0 V, at Topr = -40C to 125C unless otherwise specified)
5.5.2.8
Table 5.78
Symbol tBUF tHD;STA tLOW tR tHD;DAT tHIGH fF tsu;DAT tsu;STA tsu;STO
Multi-master I2C-bus
Multi-master I2C-bus
Parameter Bus free time Hold time in start condition Hold time in SCL clock 0 status SCL, SDA signals' rising time Data hold time Hold time in SCL clock 1 status SCL, SDA signals' falling time Data setup time Setup time in restart condition Stop condition setup time 250 4.7 4.0 0 4.0 300 Standard Clock Mode Min. 4.7 4.0 4.7 1000 Max. High-speed Clock Mode Min. 1.3 0.6 1.3 20 + 0.1 Cb 0 0.6 20 + 0.1 Cb 100 0.6 0.6 300 300 0.9 Max. Unit
s s s
ns
s s
ns ns
s s
SDA
t BUF t HD;STA t LOW
s
t su;STO
tR
tF
SCL
p
Sr
p
t HD;STA
t HD;DTA
t HIGH
t su;DTA
t su;STA
Figure 5.45
Multi-master I2C-bus
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5. Electrical Characteristics
K-Version, VCC = 5 V
Timing Requirements (VCC = 5 V, VSS = 0 V, at Topr = -40C to 125C unless otherwise specified)
5.5.2.9
Table 5.79
Symbol tc(SSCK) tw(SSCKH) tw(SSCKL) tr(SSCK)
Serial bus interface
Serial Bus Interface
Characteristic SSCK clock cycle time SSCK clock high pulse width SSCK clock low pulse width Master SSCK clock rising time Slave Master SSCK clock falling time Slave 100 1 Slave Slave 1 tCYC + 50 (1) 1 tCYC + 50 (1) 1 3.0 V VCC 5.5 V 3.0 V VCC 5.5 V 1.5 tCYC + 100 (1) 1.5 tCYC + 100 (1) 1 1 1 Measurement condition Value Min. 250 0.4 0.4 0.6 0.6 1 Typ. Max. Unit ns tc(SSCK) tc(SSCK) tCYC (1)
s
tf(SSCK)
tCYC (1)
s
tsu(SSIO-SSCK) SSO, SSI data input setup time th(SSCK-SSIO) SSO, SSI data input hold time
ns tCYC (1) ns ns tCYC (1) ns ns
tsu(SCS-SSCK) SCS setup time th(SSCK-SCS) td(SSCK-SSIO) ten(SCS-SSI) tdis(SCS-SSI) Note: 1.
SCS hold time
SS0, SSI data output delay time SSI output enable time SSI output disable time
1 tCYC is 1/f1 (s).
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5. Electrical Characteristics
K-Version, VCC = 5 V
4-Wire Bus Communication Mode, Master, CPHS = 1
VIH or VOH
SCS (output)
VIL or VOL t w(SSCKH) t f(SSCK) t r(SSCK)
SSCK (output) (CPOS = 1)
t w(SSCKL) t w(SSCKH)
SSCK (output) (CPOS = 0)
t w(SSCKL) t c(SSCK)
SSO (output)
t d(SSCK-SSIO)
SSI (input)
t su(SSIO-SSCK) t h(SSCK-SSIO)
4-Wire Bus Communication Mode, Master, CPHS = 0
VIH or VOH
SCS (output)
VIL or VOL t w(SSCKH) t f(SSCK) t r(SSCK)
SSCK (output) (CPOS = 1)
t w(SSCKL) t w(SSCKH)
SSCK (output) (CPOS =0)
t w(SSCKL) t c(SSCK)
SSO (output)
t d(SSCK-SSIO)
SSI (input)
t su(SSIO-SSCK) t h(SSCK-SSIO)
CPHS, CPOS: Bits in the SSMR register
Figure 5.46
I/O Timing of Serial Bus Interface (Master)
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5. Electrical Characteristics
K-Version, VCC = 5 V
4-Wire Bus Communication Mode, Slave, CPHS = 1
VIH or VOH
SCS (input)
VIL or VOL t su(SCS-SSCK) t w(SSCKH) t f(SSCK) t r(SSCK) t h(SSCK-SCS)
SSCK (input) (CPOS = 1)
t w(SSCKL) t w(SSCKH)
SSCK (input) (CPOS = 0)
t w(SSCKL) t c(SSCK)
SSO (input)
t su(SSIO-SSCK) t h(SSCK-SSIO)
SSI (output)
t en(SCS-SSI) t d(SSCK-SSIO) t dis(SCS-SSI)
4-Wire Bus Communication Mode, Slave, CPHS = 0 SCS (input)
VIH or VOH VIL or VOL t su(SCS-SSCK) t w(SSCKH) t f(SSCK) t r(SSCK) t h(SSCK-SCS)
SSCK (input) (CPOS = 1)
t w(SSCKL) t w(SSCKH)
SSCK (input) (CPOS = 0)
t w(SSCKL) t c(SSCK)
SSO (input)
t su(SSIO-SSCK)
t h(SSCK-SSIO)
SSI (output)
t en(SCS-SSI) t d(SSCK-SSIO) t dis(SCS-SSI)
CPHS, CPOS: Bits in the SSMR register
Figure 5.47
I/O Timing of Serial Bus Interface (Slave)
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5. Electrical Characteristics
K-Version, VCC = 5 V
t w(SSCKH) VIH or VOH
SSCK
VIL or VOL t w(SSCKL) t c(SSCK)
SSO (output)
t d(SSCK-SSIO)
SSI (input)
t su(SSIO-SSCK) t h(SSCK-SSIO)
Figure 5.48
I/O Timing of Serial Bus Interface (Synchronous Communication Mode)
MCU
Pin to be measured
30 pF
Figure 5.49
Switching Characteristic Measurement Circuit
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5. Electrical Characteristics
5.6 5.6.1
Electrical Characteristics (K-Version, VCC = 3 V) Electrical Characteristics
K-Version, VCC = 3 V
Table 5.80 Electrical Characteristics (1)
Standard Min. Typ. Max.
VCC = 3.0 to 3.6 V, VSS = 0 V at Topr = -40C to 125C, f(BCLK)=32 MHz unless otherwise specified.
Symbol Parameter P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6 to P8_7, P9_0 to P9_7, P10_0 to P10_7 XOUT HIGH POWER LOW POWER HIGH POWER LOW POWER Measuring Condition Unit
VOH
HIGH Output Voltage
IOH = -1 mA
VCC-0.5
VCC
V
HIGH Output Voltage VOH HIGH Output Voltage
IOH = -0.1 mA IOH = -50 A With no load applied With no load applied
VCC-0.5 VCC-0.5 2.5 1.6
VCC VCC
V
XCOUT
V
VOL
LOW Output Voltage
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7 XOUT HIGH POWER LOW POWER HIGH POWER LOW POWER
IOL = 1mA
0.5
V
LOW Output Voltage VOL LOW Output Voltage
IOL = 0.1mA IOL = 50A With no load applied With no load applied 0 0
0.5 0.5
V
XCOUT
V
VT+-VT-
Hysteresis
TA0IN to TA4IN, TB0IN to TB5IN, INT0 to INT7, NMI, ADTRG, CTS0 to CTS3, SCL2, SDA2, CLK0 to CLK4, TA0OUT to TA4OUT, KI0 to KI3, RXD0 to RXD4, ZP, IDU, IDW, IDV, SD, INPC1_0 to INPC1_7, SSI0, SSCK0, SCS0, LIN0IN, CRX0, CRX1
RESET
0.4VCC
V
VT+-VTVT+-VT-
Hysteresis Hysteresis
1.8 0.8
V V
XIN P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7 XIN, RESET, CNVSS P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7 XIN, RESET, CNVSS P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6 to P8_7, P9_0 to P9_7, P10_0 to P10_7
IIH
HIGH Input Current
VI = 3V
4.0
A
IIL
LOW Input Current
VI = 0V
-4.0
A
RPULLUP
Pull-Up Resistance
VI = 0V
50
100
500
k
RfXIN RfXCIN VRAM
Feedback Resistance XIN Feedback Resistance XCIN RAM Retention Voltage At stop mode 2.0
3.0 25
M M V
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5. Electrical Characteristics
K-Version, VCC = 3 V
Table 5.81 Symbol Electrical Characteristics (2) Parameter Measuring Condition
f(BCLK) = 32 MHz, XIN = 8 MHz (square wave), PLL multiply-by-8 125 kHz on-chip oscillator operates f(BCLK) = 20 MHz, High speed mode XIN = 20 MHz (square wave), 125 kHz on-chip oscillator operates f(BCLK) = 16 MHz, XIN = 16 MHz (square wave), 125 kHz on-chip oscillator operates Main clock stops 40 MHz on-chip oscillator operates 125 kHz on-chip oscillator operates 40 MHz on-chip oscillator No division mode Main clock stops 40 MHz on-chip oscillator operates 125 kHz on-chip oscillator operates Divide-by-8 Main clock stops 40 MHz on-chip oscillator stops 125 kHz on-chip oscillator 125 kHz on-chip oscillator operates mode Divide-by-8 FMR22 = FMR23 = 1 (Low-current consumption read mode) f(BCLK) = 32 kHz On ROM Low power mode FMR22 = FMR23 = 1 (Low-current consumption read mode) Main clock stops 40 MHz on-chip oscillator stops 125 kHz on-chip oscillator operates Peripheral clock operates Topr = 25C Main clock stops 40 MHz on-chip oscillator stops 125 kHz on-chip oscillator operates Peripheral clock operates Topr = 105C Main clock stops 40 MHz on-chip oscillator stops 125 kHz on-chip oscillator operates Peripheral clock operates Topr = 125C Topr = 25C Stop mode Topr = 105C Topr = 125C
Topr = -40C to 125C unless otherwise specified.
Standard Unit Min. Typ. Max.
23 43 mA
20
38
mA
16
mA
20
38
mA
6
mA
190
580
A
ICC
Power Supply Current (VCC = 3.0 V to 3.6 V) In single-chip mode, the output pins are open and other pins are VSS
200
A
25
A
Wait mode
85
A
125
A A A A
2 60 100
12
During flash memory program During flash memory erase
Idet2 Idet0 Low Voltage Detection Dissipation Current Reset Area Detection Dissipation Current
f(BCLK) = 10 MHz, PM17 = 1 (one wait) VCC = 3.0 V f(BCLK) = 10 MHz, PM17 = 1 (one wait) VCC = 3.0 V
20.0 30.0
3 6
mA mA
A A
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5. Electrical Characteristics
K-Version, VCC = 3 V
5.6.2 Timing Requirements (Peripheral Functions and Others)
(VCC = 3 V, VSS = 0 V, at Topr = -40C to 125C unless otherwise specified)
5.6.2.1
Table 5.82
Symbol tw(RSTL)
Reset Input (RESET Input)
Reset Input (RESET Input)
Parameter
RESET input low pulse width
Standard Min. 10 Max.
Unit
s
RESET input t w(RTSL)
Figure 5.50
Reset Input (RESET Input)
5.6.2.2
Table 5.83
Symbol tc tw(H) tw(L) tr tf
External Clock Input
External Clock Input (XIN input) (1)
Parameter External clock input cycle time External clock input high pulse width External clock input low pulse width External clock rise time External clock fall time Standard Min. Max. 50 20 20 9 9 Unit ns ns ns ns ns
Note: 1. The condition is VCC = 3.0V.
XIN input tr t w(H) tf tc t w(L)
Figure 5.51
External Clock Input (XIN Input)
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5. Electrical Characteristics
K-Version, VCC = 3 V
Timing Requirements (VCC = 3 V, VSS = 0 V, at Topr = -40C to 125C unless otherwise specified)
5.6.2.3
Table 5.84
Symbol tc(TA) tw(TAH) tw(TAL)
Timer A Input
Timer A Input (Counter Input in Event Counter Mode)
Parameter TAiIN input cycle time TAiIN input high pulse width TAiIN input low pulse width Standard Min. Max. 150 60 60 Unit ns ns ns
Table 5.85
Symbol tc(TA) tw(TAH) tw(TAL)
Timer A Input (Gating Input in Timer Mode)
Parameter TAiIN input cycle time TAiIN input high pulse width TAiIN input low pulse width Standard Min. Max. 600 300 300 Unit ns ns ns
Table 5.86
Symbol tc(TA) tw(TAH) tw(TAL)
Timer A Input (External Trigger Input in One-shot Timer Mode)
Parameter TAiIN input cycle time TAiIN input high pulse width TAiIN input low pulse width Standard Min. Max. 300 150 150 Unit ns ns ns
Table 5.87
Symbol tw(TAH) tw(TAL)
Timer A Input (External Trigger Input in PWM Mode, Programmable Output Mode)
Parameter TAiIN input high pulse width TAiIN input low pulse width Standard Min. Max. 150 150 Unit ns ns
tc(TA) t w(TAH) TAiIN input t w(TAL) tc(UP) t w(UPH) TAiOUT input t w(UPL)
Figure 5.52
Timer A Input
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5. Electrical Characteristics
K-Version, VCC = 3 V
Timing Requirements (VCC = 3 V, VSS = 0 V, at Topr = -40C to 125C unless otherwise specified) Table 5.88
Symbol tc(TA) tsu(TAIN-TAOUT) tsu(TAOUT-TAIN) TAiIN input cycle time TAiOUT input setup time TAiIN input setup time
Timer A Input (Two-phase Pulse Input in Event Counter Mode)
Parameter Standard Min. Max. 2 500 500 Unit
s
ns ns
Two-phase pulse input in event counter mode tc(TA) TAiIN input tsu(TAIN-TAOUT) TAiOUT input tsu(TAOUT-TAIN) tsu(TAIN-TAOUT) tsu(TAOUT-TAIN)
Figure 5.53
Timer A Input (Two-Phase Pulse Input in Event Counter Mode)
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5. Electrical Characteristics
K-Version, VCC = 3 V
Timing Requirements (VCC = 3 V, VSS = 0 V, at Topr = -40C to 125C unless otherwise specified)
5.6.2.4
Timer B Input
Table 5.89
Symbol tc(TB) tw(TBH) tw(TBL) tc(TB) tw(TBH) tw(TBL)
Timer B Input (Counter Input in Event Counter Mode)
Parameter TBiIN input cycle time (counted on one edge) TBiIN input high pulse width (counted on one edge) TBiIN input low pulse width (counted on one edge) TBiIN input cycle time (counted on both edges) TBiIN input high pulse width (counted on both edges) TBiIN Input low pulse width (counted on both edges) Standard Min. 150 60 60 300 120 120 Max. Unit ns ns ns ns ns ns
Table 5.90
Symbol tc(TB) tw(TBH) tw(TBL)
Timer B Input (Pulse Period Measurement Mode)
Parameter TBiIN input cycle time TBiIN input high pulse width TBiIN input low pulse width Standard Min. 600 300 300 Max. Unit ns ns ns
Table 5.91
Symbol tc(TB) tw(TBH) tw(TBL)
Timer B Input (Pulse Width Measurement Mode)
Parameter TBiIN input cycle time TBiIN input high pulse width TBiIN input low pulse width Standard Min. 600 300 300 Max. Unit ns ns ns
tc(TB) t w(TBH) TBiIN input t w(TBL)
Figure 5.54
Timer B Input
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5. Electrical Characteristics
K-Version, VCC = 3 V
Timing Requirements (VCC = 3 V, VSS = 0 V, at Topr = -40C to 125C unless otherwise specified)
5.6.2.5
Table 5.92
Symbol tw(TSH) tw(TSL) tsu(TSUDA-TSUDB) tsu(TSUDB-TSUDA)
Timer S Input
Timer S Input (Two-phase Pulse Input in Two-phase Pulse Signal Processing Mode)
Parameter TSUDA, TSUDB input high pulse width TSUDA, TSUDB input low pulse width TSUDB input setup time TSUDA input setup time Standard Min. Max. 2 2 1 1 Unit s s s s
Two-phase pulse input in two-phase pulse signal processing mode
tw(TSH) tw(TSL)
TSUDA input
tsu(TSUDA-TSUDB) tw(TSH) tsu(TSUDA-TSUDB) tsu(TSUDB-TSUDA) tw(TSL)
TSUDB input
tsu(TSUDB-TSUDA)
Note: 1. When the TSUDA and TSUDB phases are interchanged, tsu(TSUDA-TSUDB) and tsu(TSUDB-TSUDA) are also interchanged.
Figure 5.55
Timer S Input (Two-phase Pulse Input in Two-phase Pulse Signal Processing Mode)
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5. Electrical Characteristics
K-Version, VCC = 3 V
Timing Requirements (VCC = 3 V, VSS = 0 V, at Topr = -40C to 125C unless otherwise specified)
5.6.2.6
Table 5.93
Symbol tc(CK) tw(CKH) tw(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D)
Serial Interface
Serial Interface
Parameter CLKi input cycle time CLKi input high pulse width CLKi input low pulse width TXDi output delay time TXDi hold time RXDi input setup time RXDi input hold time 0 100 90 Standard Min. 300 150 150 160 Max. Unit ns ns ns ns ns ns ns
tc(CK) t w(CKH) CLKi t w(CKL) th(C-Q) TXDi td(C-Q) RXDi tsu(D-C) th(C-D)
Figure 5.56
Serial Interface
5.6.2.7
Table 5.94
Symbol tw(INH) tw(INL)
External Interrupt INTi Input
External Interrupt INTi Input
Parameter
INTi Input HIGH Pulse Width INTi Input LOW Pulse Width
Standard Min. 380 380 Max.
Unit ns ns
t w(INL) INTi input t w(INH)
Figure 5.57
External Interrupt INTi Input
REJ03B0267-0101 Jul 23, 2010
Rev.1.01
Page 151 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
K-Version, VCC = 3 V
Timing Requirements (VCC = 3 V, VSS = 0 V, at Topr = -40C to 125C unless otherwise specified)
5.6.2.8
Table 5.95
Symbol tBUF tHD;STA tLOW tR tHD;DAT tHIGH fF tsu;DAT tsu;STA tsu;STO
Multi-master I2C-bus
Multi-master I2C-bus
Parameter Bus free time Hold time in start condition Hold time in SCL clock 0 status SCL, SDA signals' rising time Data hold time Hold time in SCL clock 1 status SCL, SDA signals' falling time Data setup time Setup time in restart condition Stop condition setup time 250 4.7 4.0 0 4.0 300 Standard Clock Mode Min. 4.7 4.0 4.7 1000 Max. High-speed Clock Mode Min. 1.3 0.6 1.3 20 + 0.1 Cb 0 0.6 20 + 0.1 Cb 100 0.6 0.6 300 300 0.9 Max. Unit
s s s
ns
s s
ns ns
s s
SDA
t BUF t HD;STA t LOW
s
t su;STO
tR
tF
SCL
p
Sr
p
t HD;STA
t HD;DTA
t HIGH
t su;DTA
t su;STA
Figure 5.58
Multi-master I2C-bus
REJ03B0267-0101 Jul 23, 2010
Rev.1.01
Page 152 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
K-Version, VCC = 3 V
Timing Requirements (VCC = 3 V, VSS = 0 V, at Topr = -40C to 125C unless otherwise specified)
5.6.2.9
Table 5.96
Symbol tc(SSCK) tw(SSCKH) tw(SSCKL) tr(SSCK)
Serial bus interface
Serial Bus Interface
Characteristic SSCK clock cycle time SSCK clock high pulse width SSCK clock low pulse width Master SSCK clock rising time Slave Master SSCK clock falling time Slave 100 1 Slave Slave 1 tCYC + 50 (1) 1 tCYC + 50 (1) 1 3.0 V VCC 5.5 V 3.0 V VCC 5.5 V 1.5 tCYC + 100 (1) 1.5 tCYC + 100 (1) 1 1 1 Measurement condition Value Min. 250 0.4 0.4 0.6 0.6 1 Typ. Max. Unit ns tc(SSCK) tc(SSCK) tCYC (1)
s
tf(SSCK)
tCYC (1)
s
tsu(SSIO-SSCK) SSO, SSI data input setup time th(SSCK-SSIO) SSO, SSI data input hold time
ns tCYC (1) ns ns tCYC (1) ns ns
tsu(SCS-SSCK) SCS setup time th(SSCK-SCS) td(SSCK-SSIO) ten(SCS-SSI) tdis(SCS-SSI) Note: 1.
SCS hold time
SS0, SSI data output delay time SSI output enable time SSI output disable time
1 tCYC is 1/f1 (s).
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Rev.1.01
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M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
K-Version, VCC = 3 V
4-Wire Bus Communication Mode, Master, CPHS = 1
VIH or VOH
SCS (output)
VIL or VOL t w(SSCKH) t f(SSCK) t r(SSCK)
SSCK (output) (CPOS = 1)
t w(SSCKL) t w(SSCKH)
SSCK (output) (CPOS = 0)
t w(SSCKL) t c(SSCK)
SSO (output)
t d(SSCK-SSIO)
SSI (input)
t su(SSIO-SSCK) t h(SSCK-SSIO)
4-Wire Bus Communication Mode, Master, CPHS = 0
VIH or VOH
SCS (output)
VIL or VOL t w(SSCKH) t f(SSCK) t r(SSCK)
SSCK (output) (CPOS = 1)
t w(SSCKL) t w(SSCKH)
SSCK (output) (CPOS =0)
t w(SSCKL) t c(SSCK)
SSO (output)
t d(SSCK-SSIO)
SSI (input)
t su(SSIO-SSCK) t h(SSCK-SSIO)
CPHS, CPOS: Bits in the SSMR register
Figure 5.59
I/O Timing of Serial Bus Interface (Master)
REJ03B0267-0101 Jul 23, 2010
Rev.1.01
Page 154 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
K-Version, VCC = 3 V
4-Wire Bus Communication Mode, Slave, CPHS = 1
VIH or VOH
SCS (input)
VIL or VOL t su(SCS-SSCK) t w(SSCKH) t f(SSCK) t r(SSCK) t h(SSCK-SCS)
SSCK (input) (CPOS = 1)
t w(SSCKL) t w(SSCKH)
SSCK (input) (CPOS = 0)
t w(SSCKL) t c(SSCK)
SSO (input)
t su(SSIO-SSCK) t h(SSCK-SSIO)
SSI (output)
t en(SCS-SSI) t d(SSCK-SSIO) t dis(SCS-SSI)
4-Wire Bus Communication Mode, Slave, CPHS = 0 SCS (input)
VIH or VOH VIL or VOL t su(SCS-SSCK) t w(SSCKH) t f(SSCK) t r(SSCK) t h(SSCK-SCS)
SSCK (input) (CPOS = 1)
t w(SSCKL) t w(SSCKH)
SSCK (input) (CPOS = 0)
t w(SSCKL) t c(SSCK)
SSO (input)
t su(SSIO-SSCK)
t h(SSCK-SSIO)
SSI (output)
t en(SCS-SSI) t d(SSCK-SSIO) t dis(SCS-SSI)
CPHS, CPOS: Bits in the SSMR register
Figure 5.60
I/O Timing of Serial Bus Interface (Slave)
REJ03B0267-0101 Jul 23, 2010
Rev.1.01
Page 155 of 156
M16C/5M Group, M16C/57 Group
5. Electrical Characteristics
K-Version, VCC = 3 V
t w(SSCKH) VIH or VOH
SSCK
VIL or VOL t w(SSCKL) t c(SSCK)
SSO (output)
t d(SSCK-SSIO)
SSI (input)
t su(SSIO-SSCK) t h(SSCK-SSIO)
Figure 5.61
I/O Timing of Serial Bus Interface (Synchronous Communication Mode)
MCU
Pin to be measured
30 pF
Figure 5.62
Switching Characteristic Measurement Circuit
REJ03B0267-0101 Jul 23, 2010
Rev.1.01
Page 156 of 156
REVISION HISTORY
Rev. 1.01 Date Jul 23, 2010
M16C/5M Group Datasheet
Description Summary First edition issued
Page --
All trademarks and registered trademarks are the property of their respective owners.
A- 1
General Precautions in the Handling of MPU/MCU Products
The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence. 1. Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual. The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. Unused pins should be handled as described under Handling of Unused Pins in the manual. 2. Processing at Power-on The state of the product is undefined at the moment when power is supplied. The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited. The reserved addresses are provided for the possible future expansion of functions. Do not access these addresses; the correct operation of LSI is not guaranteed if they are accessed. 4. Clock Signals After applying a reset, only release the reset line after the operating clock signal has become stable. When switching the clock signal during program execution, wait until the target clock signal has stabilized. When the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. Differences between Products Before changing from one product to another, i.e. to one with a different part number, confirm that the change will not lead to problems. The characteristics of MPU/MCU in the same group but having different part numbers may differ because of the differences in internal memory capacity and layout pattern. When changing to products of different part numbers, implement a system-evaluation test for each of the products.
Notice
1. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website. 2. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or others. 3. 4. You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 5. When exporting the products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. You should not use Renesas Electronics products or the technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the development of weapons of mass destruction. Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. 6. Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics does not warrant that such information is error free. Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein. 7. Renesas Electronics products are classified according to the following three quality grades: "Standard", "High Quality", and "Specific". The recommended applications for each Renesas Electronics product depends on the product's quality grade, as indicated below. You must check the quality grade of each Renesas Electronics product before using it in a particular application. You may not use any Renesas Electronics product for any application categorized as "Specific" without the prior written consent of Renesas Electronics. Further, you may not use any Renesas Electronics product for any application for which it is not intended without the prior written consent of Renesas Electronics. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as "Specific" or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics. The quality grade of each Renesas Electronics product is "Standard" unless otherwise expressly specified in a Renesas Electronics data sheets or data books, etc. "Standard": Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots. "High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-crime systems; safety equipment; and medical equipment not specifically designed for life support. "Specific": Aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or systems for life support (e.g. artificial life support devices or systems), surgical implantations, or healthcare intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life. 8. 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Please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 10. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. 11. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of Renesas Electronics. 12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries. (Note 1) (Note 2) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majority-owned subsidiaries. "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics.
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